Abstract:
PURPOSE: A low power and high density source driver and a current driven active matrix organic electroluminescence device provided with the same are provided to increase the degree of integration by operating the inner circuits of the driver with a normal voltage. CONSTITUTION: A low power and high density source driver includes a shift register unit(310), a data latch unit(320), a line latch unit(330), a current digital-to-analog converter(340) and a high voltage protection unit(350). The shift register unit outputs the enable signal for storing the data. The data latch unit stores the digital data inputted from outside. The line latch unit outputs the stored data in parallel simultaneously. The current digital-to-analog converter converts the digital signal outputted from the line latch unit and outputs the converted signal as the current signal. And, the high voltage protection unit transmits the outputs the outputs of the current digital-to-analog converter to the source line of the external panel and protects the inner circuits from the high voltage of the panel side.
Abstract:
본 발명의 마이크로 컨트롤러를 위한 데이터 버스 시스템은, 입/출력부, 중앙 처리 장치, 내부 메모리 및 주변 회로부를 포함하는 마이크로 컨트롤러를 위한 데이터 버스 시스템에 관한 것이다. 이 데이터 버스 시스템은, 중앙 처리 장치로부터 나가는 데이터와 외부로부터 입/출력부 또는 내부 메모리로 들어가는 데이터에 의해 사용되는 외부 억세스 버스와, 중앙 처리 장치로 들어가는 데이터와 입/출력부 또는 내부 메모리로부터 나가는 데이터와, 그리고 주변 회로부로 들어가거나 주변 회로부로부터 나가는 데이터에 의해 사용되는 내부 억세스 버스, 및 내부 메모리가 입/출력부로 통해 나가는 데이터에 의해 사용되는 내부 메모리 테스트 버스를 구비한다.
Abstract:
PURPOSE: A method for fabricating a power IC using an SOI substrate is provided to enhance resolution of a display unit by improving and optimizing the accuracy of a fabrication process. CONSTITUTION: A first trench(34a) and a second trench(34b) are formed by etching partially an SOI substrate(31). A well of an LDMOS element, a floating region, and a well of a CMOS element are formed within the SOI substrate. The first and the second field oxide layer(42a,42b) are buried into the first and the second trenches. A third field oxide layer(42c) is formed on the floating region. A thick gate insulating layer(45a) of the LDMOS element and a thin gate insulating layer(45b) of the CMOS element are formed thereon. A gate electrode(46a) of the LDMOS element and gate electrodes(46b,46c) of the CMOS element are formed simultaneously. An LDD region of the LDMOS element and an LDD region of the CMOS element are formed within the SOI substrate of both sides of the gate electrodes. Spacers are formed on sidewalls of the gate electrodes, respectively. A source region of the LDMOS element and a source/drain region of the CMOS element are formed, respectively.
Abstract:
PURPOSE: A method for fabricating a semiconductor device is provided to be compatible with a process for fabricating an analog CMOS(complementary-metal-oxide-semiconductor) device of a sub micron class by forming sources and drains of high and low voltage devices in a well region formed in a silicon device region of a SOI(silicon-on-insulator) substrate. CONSTITUTION: The silicon device region(3) is patterned to respectively form a trench in an isolation region and a capacitor formation region between high and low voltage device regions. A drift region of the first conductivity type is formed in the silicon device region of the high voltage device region. Wells of the second and first conductivity types are formed in the drift region and the silicon device region of the high and low voltage device regions. An isolation layer(10) is formed in the trench. A field oxide layer(11) is formed in the silicon device region of the high voltage device region. Channel ions are implanted into the silicon device region of the high and low voltage device regions. Thick and thin gate oxide layers are formed in the high and low voltage device regions, respectively. A gate electrode(14a,14b) is formed on the channel region of the high and low voltage device regions while a lower electrode(14c) is formed in the capacitor formation region. Sources and drains(17a,17b) are formed in the wells of the high and low voltage device regions. An insulation layer(18) and an upper electrode(19) are sequentially formed on the lower electrode of the capacitor formation region.
Abstract:
PURPOSE: A method for fabricating a power IC using an SOI substrate is provided to enhance resolution of a display unit by improving and optimizing the accuracy of a fabrication process. CONSTITUTION: A first trench(34a) and a second trench(34b) are formed by etching partially an SOI substrate(31). A well of an LDMOS element, a floating region, and a well of a CMOS element are formed within the SOI substrate. The first and the second field oxide layer(42a,42b) are buried into the first and the second trenches. A third field oxide layer(42c) is formed on the floating region. A thick gate insulating layer(45a) of the LDMOS element and a thin gate insulating layer(45b) of the CMOS element are formed thereon. A gate electrode(46a) of the LDMOS element and gate electrodes(46b,46c) of the CMOS element are formed simultaneously. An LDD region of the LDMOS element and an LDD region of the CMOS element are formed within the SOI substrate of both sides of the gate electrodes. Spacers are formed on sidewalls of the gate electrodes, respectively. A source region of the LDMOS element and a source/drain region of the CMOS element are formed, respectively.
Abstract:
PURPOSE: An input/output port circuit is provided, which is driven by high supply voltage and low supply voltage at the same time, and reduces power consumption by selectivly driving the input/output port circuit. CONSTITUTION: A signal register(22) stores output signals, and an input/output register(23) stores an input/output control signal determining an input/output direction. A power supply switch circuit(21) supplies a high voltage or a low voltage selectively according to a control signal. A signal control circuit(24) determines a direction of a signal according to a value of the signal register and a value of the input/output register. An output control circuit(25) is driven according to a value of the control register and an output of the signal control circuit. And an output driver circuit(26) outputs the low voltage and the high voltage or a ground value according to outputs of the signal control circuit and the output control circuit. The input/output port circuit comprises a number of output control registers(27).
Abstract:
PURPOSE: A multi-output DC-DC converter is provided to be capable of outputting a multi-level voltage using one embedded inductor having a plurality of output taps. CONSTITUTION: An inductor part(300) is supplied with an input voltage and has a plurality of output taps which are spaced apart from each other. The first switching unit(230) consists of a plurality of transistors cascaded between each output tap of the inductor part and a common node and controlled by corresponding control signals. The second switching unit(210) is connected between the common node and the output terminal and is controlled by the control signal. The third switching unit(220) consists of a plurality of transistors which are connected in parallel between the common node and a ground voltage and are selectively operated according to corresponding control signals.
Abstract:
A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.
Abstract:
PURPOSE: A method for fabricating a power IC is provided to reduce an isolation area by forming a nitride layer between a trench oxide layer and a polysilicon layer or performing a trench isolation process using the nitride layer and the polysilicon instead of the trench oxide layer. CONSTITUTION: An oxide layer and a photoresist layer are sequentially on a silicon layer(102). The photoresist layer is patterned by using a trench mask. The oxide layer is patterned by using the patterned photoresist layer as a mask. The remaining photoresist is removed therefrom. The trench is etched by using the patterned oxide layer as the mask and a trench is formed thereby. A nitride layer(134) is formed on an upper surface of the resultant including the trench. The trench is buried by depositing a polysilicon thereon. An isolation layer is formed by removing the polysilicon and the nitride layer.
Abstract:
PURPOSE: A method for fabricating a power integrated circuit is provided to remarkably reduce a high temperature annealing process for fabricating the power integrated circuit, by mixing a non-reduced surface field(RESURF) n-lateral double diffused metal oxide semiconductor(LDMOS) transistor and a RESURF p-LDMOS transistor. CONSTITUTION: The power integrated circuit includes the RESURF LDMOS transistor using a silicon-on-insulator, the non-RESURF LDMOS transistor of an opposite type to the RESURF LDMOS transistor and a logic complementary metal oxide semiconductor(CMOS). The regions where the logic CMOS as a low voltage device and an LDMOS transistor as a high power device are fabricated are doped with the same impurity type in a silicon substrate.