公开(公告)号：EP1330838B1

公开(公告)日：2010-12-01

申请号：EP01957270.0

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AMINPUR, Massud ,  WU, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer (510) above a substrate layer ((505), forming a gate conductor layer (515) above the gate dielectric layer (510), forming a first hard mask layer (540). The method also includes forming a trimmed photoresist mark (570) above the second hard mask layer (550), and forming a patterned hard mask (650) in the second hard mask layer (550) using the trimmed photoresist mask (570) to remove portions (655) of the second hard mask layer (550), the patterned hard mask (650) having a first dimension (δtrim). The method further includes forming a selectively etched hard mask (740) in the first hard mask layer (540) by removing portions (745) of the first hard mask layer (540) adjacent the patterned hard mask (650), the selectively etched hard mask (740) having a second dimension (Δ) less than the first dimension (δtrim), and forming a structure (800) using the selectively etched hard mask (740) to remove portions of the gate conductor layer (515) above the gate dielectric layer (510).

公开(公告)号：EP1456877B1

公开(公告)日：2010-07-21

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

公开(公告)号：EP0795199B1

公开(公告)日：2005-11-09

申请号：EP95942471.4

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PRAMANICK, Shekhar ,  LUNING, Scott ,  FEWKES, Jonathan

IPC: H01L21/027 ,  H01L21/321

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/32137

Abstract: A structure for patterning a polysilicon layer includes a TiN layer located above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is located above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.

公开(公告)号：EP1456877A1

公开(公告)日：2004-09-15

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.

公开(公告)号：EP1206798A1

公开(公告)日：2002-05-22

申请号：EP00916317.1

申请日：2000-03-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： ISHIDA, Emi ,  LUNING, Scott ,  THURGATE, Tim

IPC: H01L21/336 ,  H01L21/28

CPC classification number: H01L29/66583 ,  H01L21/26586 ,  H01L21/28141 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  Y10S438/947

Abstract: A narrow groove is formed over a substrate. To form such a narrow groove, a first material is formed over a substrate, the first material having a sidewall. A spacer is formed abutting the sidewall. Subsequently a second material is formed adjacent to the spacer. The spacer is removed leaving a groove between the first material and second material. In one embodiment, the groove is filled with material for a narrow feature, such as a gate, and the first material and second material are removed. As a result a gate or other narrow feature is formed having a length defined by the width of a spacer. In another embodiment, an implant is performed through the small groove, resulting in a small localized implant.

公开(公告)号：EP1330838A1

公开(公告)日：2003-07-30

申请号：EP01957270.0

申请日：2001-07-26

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： AMINPUR, Massud ,  WU, David ,  LUNING, Scott

IPC: H01L21/28

CPC classification number: H01L21/28123 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric layer (510) above a substrate layer ((505), forming a gate conductor layer (515) above the gate dielectric layer (510), forming a first hard mask layer (540). The method also includes forming a trimmed photoresist mark (570) above the second hard mask layer (550), and forming a patterned hard mask (650) in the second hard mask layer (550) using the trimmed photoresist mask (570) to remove portions (655) of the second hard mask layer (550), the patterned hard mask (650) having a first dimension (δtrim). The method further includes forming a selectively etched hard mask (740) in the first hard mask layer (540) by removing portions (745) of the first hard mask layer (540) adjacent the patterned hard mask (650), the selectively etched hard mask (740) having a second dimension (Δ) less than the first dimension (δtrim), and forming a structure (800) using the selectively etched hard mask (740) to remove portions of the gate conductor layer (515) above the gate dielectric layer (510).

公开(公告)号：EP0795199A1

公开(公告)日：1997-09-17

申请号：EP95942471.0

申请日：1995-11-22

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： PRAMANICK, Shekhar ,  LUNING, Scott ,  FEWKES, Jonathan

IPC: G03F7 ,  H01L21

CPC classification number: G03F7/091 ,  H01L21/0276 ,  H01L21/32137

Abstract: A structure for patterning a polysilicon layer includes a TiN layer located above an amorphous silicon (a-Si) layer forming a TiN/a-Si stack. The TiN/a-Si stack is located above the polysilicon layer. The TiN layer serves as an ARC to reduce overexposure of the photoresist used to pattern the polysilicon layer, while the a-Si layer prevents contamination of the layer below the polysilicon layer.