公开(公告)号：WO1998025182A1

公开(公告)日：1998-06-11

申请号：PCT/US1997022616

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70433 ,  G03F1/70 ,  G03F7/70241

Abstract: A reticle (130) provides an image pattern and compensates for a lens error in a photolithographic system. The reticle is structurally modified using image displacement data indicative of the lens error. The reticle can be structurally modified by adjusting the configuration (or layout) of radiation-transmitting regions (132, 134) for instance by adjusting a chrome pattern on the top surface of a quartz base. Alternatively, the reticle can be structurally modified by adjusting the curvature of the reticle, for instance by providing a chrome pattern on the top surface of a quartz base and grinding away portions of the bottom surface of the quartz base. The image displacement data may also vary as a function of lens heating so that the reticle compensates for lens heating associated with the reticle pattern.

Abstract translation: 掩模版（130）提供图像图案并补偿光刻系统中的透镜误差。 使用指示透镜误差的图像位移数据对结构上的掩模版进行修改。 通过调节辐射透射区域（132,134）的配置（或布局），例如通过调节石英基底的顶表面上的铬图案，可以对掩模版进行结构上的修改。 或者，可以通过调整掩模版的曲率来结构地修改掩模版，例如通过在石英基底的顶表面上提供铬图案并研磨掉石英基底的底表面的部分。 图像位移数据也可以根据透镜加热而变化，使得掩模版补偿与标线图案相关联的透镜加热。

公开(公告)号：WO1997050112A1

公开(公告)日：1997-12-31

申请号：PCT/US1997002389

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim, Jr.

IPC: H01L21/02

CPC classification number: G03F7/70466 ,  G03F7/2022 ,  G03F7/70475 ,  H01L21/0334

Abstract: A method of selectively exposing a material over a substrate is disclosed. The method includes forming a material over a semiconductor substrate, forming a photosensitive layer over the material, projecting a first image pattern onto the photosensitive layer that defines a first boundary for the material, projecting a second image pattern onto the photosensitive layer after projecting the first image pattern such that the second image pattern partially overlaps the first image pattern and defines a second boundary for the material, and removing portions of the photosensitive layer corresponding to the first and second image patterns. Preferably, the first and second image patterns are essentially identical to and laterally shifted with respect to one another. In this manner, the photosensitive layer selectively exposes the material adjacent to the first and second boundaries while covering the material between the first and second boundaries, and the distance between the first and second boundaries decreases as the overlap between the first and second image patterns decreases. Advantageously, the first and second boundaries can be closer than the minimum resolution of the photolithographic system used to pattern the photosensitive layer.

Abstract translation: 公开了一种在衬底上选择性地暴露材料的方法。 该方法包括在半导体衬底上形成材料，在材料上形成感光层，将第一图案图案投射到限定材料的第一边界的光敏层上，将第一图像图案投射到感光层上， 图像图案，使得第二图像图案部分地与第一图像图案重叠并且限定材料的第二边界，以及去除与第一和第二图像图案相对应的感光层的部分。 优选地，第一和第二图像图案基本上彼此相同并且相对于彼此横向移位。 以这种方式，感光层选择性地暴露与第一和第二边界相邻的材料，同时覆盖第一和第二边界之间的材料，并且第一和第二边界之间的距离随着第一和第二图像图案之间的重叠减小而减小 。 有利地，第一和第二边界可以比用于图案感光层的光刻系统的最小分辨率更接近。

公开(公告)号：WO2003054969A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041330

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  XIANG, Qi ,  WRISTERS, Derick, J.

IPC: H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/42376 ,  H01L29/66484 ,  H01L29/6656

Abstract: High-speed MOS transistors (32) are provided by forming a conductive layer (24) embedded in transistor gate sidewall spacers (27). The embedded conductive layer (24) is electrically insulated from the gate electrode (18) and the source/drain regions (28) of the transistor (32). The embedded conductive layer (24) is positioned over the source/drain extensions (30) and causes charge to accumulate in the source/drain extensions (30) lowering the series resistance of the source/drain regions (28).

Abstract translation: 高速MOS晶体管（32）通过形成嵌入在晶体管栅极侧壁间隔物（27）中的导电层（24）来提供。 嵌入式导电层（24）与晶体管（32）的栅电极（18）和源/漏区（28）电绝缘。 嵌入式导电层（24）位于源极/漏极延伸部分（30）上方，并使电荷累积在源极/漏极延伸部（30）中，从而降低源极/漏极区域（28）的串联电阻。

公开(公告)号：WO2003054952A1

公开(公告)日：2003-07-03

申请号：PCT/US2002/041331

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

Abstract: Semiconductor devices with improved transistor performance are fabricated by forming a composite oxide/nitride liner (24,25) under a gate electrode sidewall spacer (40). Embodiements include depositing a conformal oxide layer (24) by decoupled plasma deposition, depositing a conformal nitride layer (25) by decoupled plasma deposition, depositing a spacer layer (30) and then etching.

Abstract translation: 具有改善的晶体管性能的半导体器件通过在栅电极侧壁间隔物（40）下形成复合氧化物/氮化物衬垫（24,25）来制造。 实例包括通过解耦等离子体沉积沉积保形氧化物层（24），通过解耦等离子体沉积沉积共形氮化物层（25），沉积间隔层（30）然后蚀刻。

公开(公告)号：WO1998025183A1

公开(公告)日：1998-06-11

申请号：PCT/US1997023139

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70058 ,  G03F7/70591 ,  G03F7/70891

Abstract: A method of inspecting a lens (16) includes projecting a first amount of radiation through a first test pattern (42, 44) and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern (52, 54) and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.

Abstract translation: 检查透镜（16）的方法包括：通过第一测试图案（42,44）和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，投射第二量的辐射 通过第二测试图案（52,54）和透镜提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据 。 以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。 该方法非常适合于光刻系统，如步进和重复系统。

公开(公告)号：WO1998002918A1

公开(公告)日：1998-01-22

申请号：PCT/US1997005176

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  DUANE, Michael, P. ,  WRISTERS, Derick, J.

IPC: H01L21/336

CPC classification number: H01L29/66659 ,  H01L29/7835

Abstract: A method for fabrication of a non-symmetrical LDD-IGFET is described. In one embodiment, the method includes providing a semiconductor substrate having a gate insulator (104) and a gate electrode (106), the gate electrode having opposing first and second sidewalls (103, 105) defining the length of the gate electrode and a top surface. Lightly doped source (108) and drain (110) regions are implanted into the semiconductor substrate and are substantially aligned with the sidewalls of the gate electrode. After implanting the lightly doped regions, first and second spacers (112, 114) are formed adjacent to the first and second sidewalls of the gate electrode. After forming the spacers, a portion of the gate electrode is removed to form a third sidewall (117) of the gate electrode opposite the second sidewall (105), thereby eliminating the first sidewall and reducing the length of the gate electrode. After removing the first spacer, heavily doped source (120) and drain (118) regions are implanted into the semiconductor substrate. The heavily doped drain region is substantially aligned with the outer edge of the second spacer, a portion of the lightly doped drain regions is protected beneath the second spacer, and the heavily doped source region is substantially aligned with the third sidewall. In another embodiment, the heavily doped drain region is implanted after the spacers are formed but before the third sidewall is formed and the heavily doped source region is implanted after forming the third sidewall.

Abstract translation: 描述了一种用于制造非对称LDD-IGFET的方法。 在一个实施例中，该方法包括提供具有栅极绝缘体（104）和栅电极（106）的半导体衬底，所述栅电极具有限定栅电极的长度的相对的第一和第二侧壁（103,105） 表面。 将轻掺杂源（108）和漏极（110）区域注入到半导体衬底中并且基本上与栅电极的侧壁对准。 在注入轻掺杂区域之后，第一和第二间隔物（112,114）邻近栅电极的第一和第二侧壁形成。 在形成间隔物之后，去除栅电极的一部分以形成与第二侧壁（105）相对的栅电极的第三侧壁（117），由此消除第一侧壁并减小栅电极的长度。 在去除第一间隔物之后，将重掺杂的源极（120）和漏极（118）区域注入到半导体衬底中。 重掺杂漏极区域基本上与第二间隔物的外边缘对准，轻掺杂漏极区域的一部分被保护在第二间隔物下方，并且重掺杂源极区域基本上与第三侧壁对准。 在另一个实施例中，在形成间隔物之后但在形成第三侧壁之前注入重掺杂漏极区，并且在形成第三侧壁之后注入重掺杂源极区。

公开(公告)号：WO1998002913A2

公开(公告)日：1998-01-22

申请号：PCT/US1997005089

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  GARDNER, Mark, I. ,  WRISTERS, Derick, J. ,  FULFORD, H., Jim

IPC: H01L21/033

CPC classification number: G03F7/70466 ,  G03F7/00 ,  H01L21/0337 ,  Y10S438/947

Abstract: A method of forming a gate electrode for an insulated-gatefield-effectransistor (IGFET) is disclosed. The method includes forming a gate material for providing a gate electrode over a semiconductor substrate, forming a first mask over the gate material wherein the first mask includes an opening that defines a first edge of the gate electrode, removing a first portion of the gate material to form the first edge of the gate electrode as defined by the first mask, forming a second mask over the gate material after removing the first mask wherein the second mask includes an opening that defines a second edge of the gate electrode, removing a second portion of the gate material to form the second edge of the gate electrode as defined by the second mask, and removing the second mask. Thus, the gate electrode is defined by a lateral displacement between the openings in the first and second masks. Preferably, the first and second masks are photoresist, and the length between the first and second edges of the gate electrode is less than the minimum resolution of a photolithographic system used to pattern the masks.

Abstract translation: 公开了一种形成绝缘栅场效应晶体管（IGFET）的栅电极的方法。 该方法包括形成用于在半导体衬底上提供栅电极的栅极材料，在栅极材料上形成第一掩模，其中第一掩模包括限定栅电极的第一边缘的开口，去除栅极材料的第一部分 以形成由第一掩模限定的栅电极的第一边缘，在去除第一掩模之后在栅极材料上形成第二掩模，其中第二掩模包括限定栅电极的第二边缘的开口，去除第二部分 以形成由第二掩模限定的栅电极的第二边缘，并且移除第二掩模。 因此，栅电极由第一和第二掩模中的开口之间的横向位移限定。 优选地，第一和第二掩模是光致抗蚀剂，并且栅电极的第一和第二边缘之间的长度小于用于对掩模进行图案化的光刻系统的最小分辨率。

公开(公告)号：EP1456877B1

公开(公告)日：2010-07-21

申请号：EP02796042.6

申请日：2002-12-19

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： BULLER, James, F. ,  WU, David ,  LUNING, Scott ,  WRISTERS, Derick, J. ,  KADOSH, Daniel

IPC: H01L21/336 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/6656 ,  H01L29/6659

公开(公告)号：EP1552554A2

公开(公告)日：2005-07-13

申请号：EP03799836.6

申请日：2003-10-14

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： WRISTERS, Derick, J. ,  XIANG, Qi ,  BULLER, James, F.

IPC: H01L21/762

CPC classification number: H01L29/78696 ,  H01L29/1054 ,  H01L29/66772 ,  H01L29/7846 ,  H01L29/78603

Abstract: A semiconductor device is provided with the high-speed capabilities of silicon on insulator (SOI) and strained silicon technologies, without requiring the formation of a silicon germanium layer. A layer of compressive material (22) is formed on a SOI semiconductor substrate (20) to induce strain in the overlying silicon layer (21). The compressive materials include silicon oxynitride, phosphorus, silicon nitride, and boron/phosphorus doped silica glass.

公开(公告)号：EP0978141A1

公开(公告)日：2000-02-09

申请号：EP98912999.4

申请日：1998-03-19

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： HAUSE, Frederick, N. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/8238

CPC classification number: H01L21/823814

Abstract: A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.