公开(公告)号：WO2023019070A1

公开(公告)日：2023-02-16

申请号：PCT/US2022/074392

申请日：2022-08-01

Applicant: APPLE INC.

Inventor： RAMACHANDRAN, Vidhya ,  DABRAL, Sanjay ,  JANGAM, SivaChandra ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/29 ,  H01L21/56 ,  H01L21/78

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：WO2022108776A1

公开(公告)日：2022-05-27

申请号：PCT/US2021/058397

申请日：2021-11-08

Applicant: APPLE INC.

Inventor： SHANMUGAM, Karthik ,  CARSON, Flynn P. ,  ZHAI, Jun ,  CAMENFORTE, Raymundo M. ,  LI, Menglu

IPC: H01L23/538 ,  H01L21/683 ,  H01L23/00

Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.

公开(公告)号：WO2021158419A1

公开(公告)日：2021-08-12

申请号：PCT/US2021/015441

申请日：2021-01-28

Applicant: APPLE INC.

Inventor： DABRAL, Sanjay ,  CAO, Zhitao ,  HU, Kunzhong ,  ZHAI, Jun

IPC: H01L23/50 ,  H01L23/538

Abstract: Electronic package structures and systems are described in which a 3D interconnect structure is integrated into a package redistribution layer and/or chiplet for power and signal delivery to a die. Such structures may significantly improve input output (IO) density and routing quality for signals, while keeping power delivery feasible.

公开(公告)号：WO2020112504A1

公开(公告)日：2020-06-04

申请号：PCT/US2019/062701

申请日：2019-11-21

Applicant: APPLE INC.

Inventor： ZHONG, Chonghua ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/00

Abstract: Double side mounted package structures and memory modules incorporating such double side mounted package structures are described in which memory packages are mounted on both sides of a module substrate. A routing substrate is mounted to a bottom side of the module substrate to provide general purpose in/out routing and power routing, while signal routing from the logic die to double side mounted memory packages is provided in the module routing. In an embodiment, module substrate is a coreless module substrate and may be thinner than the routing substrate.

公开(公告)号：WO2016081182A1

公开(公告)日：2016-05-26

申请号：PCT/US2015/058474

申请日：2015-10-30

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong ,  CARSON, Flynn P.

IPC: H01L25/03 ,  H01L21/98 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/525 ,  H01L23/552 ,  H01L24/19 ,  H01L24/89 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/80001 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2224/81

Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the second routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.

Abstract translation: 描述了扇出晶片级封装（FOWLP）和形成方法。 在一个实施例中，包装包括第一布线层，第一布线层的顶侧上的第一管芯，以及将第一管芯封装在第一布线层上的第一模制化合物。 第一多个导电柱从第一路由层的底侧延伸。 第二管芯位于第二布线层的顶侧，并且第一多个导电柱位于第二布线层的顶侧。 第二模塑料在第二路由层上封装第一模塑料，第一路由层，第一多个导电柱和第二模。 在一个实施例中，多个导电凸块（例如焊球）从第二布线层的底侧延伸。

公开(公告)号：WO2015020836A3

公开(公告)日：2015-02-12

申请号：PCT/US2014/048603

申请日：2014-07-29

Applicant: APPLE INC.

Inventor： ZERBE, Jared L. ,  FANG, Emerson S. ,  ZHAI, Jun ,  SEARLES, Shawn

IPC: H01L25/16 ,  H01L23/64 ,  H01G4/228 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device (120) may include one or more current consuming elements. A passive device (100) may be coupled (110) to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures (102) on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals (110). The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

公开(公告)号：WO2021236396A1

公开(公告)日：2021-11-25

申请号：PCT/US2021/032047

申请日：2021-05-12

Applicant: APPLE INC.

Inventor： CHEN, Wei ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/10 ,  H01L23/051 ,  H01L25/16

Abstract: Electronic packages and modules are described. In an embodiment, a hybrid thermal interface material including materials with different thermal conductivities is used to attach a lid to a device. In an embodiment, a low temperature solder material is included as part of an adhesion layer for attachment with a stiffener structure.

公开(公告)号：WO2021080875A1

公开(公告)日：2021-04-29

申请号：PCT/US2020/056102

申请日：2020-10-16

Applicant: APPLE INC.

Inventor： ZHAI, Jun

IPC: H01L25/065 ,  H01L25/10

Abstract: Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.

公开(公告)号：WO2017034654A1

公开(公告)日：2017-03-02

申请号：PCT/US2016/037690

申请日：2016-06-15

Applicant: APPLE INC.

Inventor： LAI, Kwan-Yu ,  ZHAI, Jun ,  HU, Kunzhong

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/7684 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/80 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/181 ,  H01L2924/186

Abstract: Packages and 3D die stacking processes are described. In an embodiment, a package includes a second level die hybrid bonded to a first package level including a first level die encapsulated in an oxide layer, and a plurality of through oxide vias (TOVs) extending through the oxide layer. In an embodiment, the TOVs and the first level die have a height of about 20 microns or less.

Abstract translation: 描述了封装和3D裸片堆叠过程。 在一个实施例中，封装包括结合到包括封装在氧化物层中的第一级管芯的第一封装级的第二级管芯晶体管和延伸穿过氧化物层的多个通孔氧化物通孔（TOV）。 在一个实施例中，TOV和第一级模具具有大约20微米或更小的高度。

公开(公告)号：WO2016171805A1

公开(公告)日：2016-10-27

申请号：PCT/US2016/021405

申请日：2016-03-08

Applicant: APPLE INC.

Inventor： ZHAI, Jun ,  HU, Kunzhong

IPC: H01L21/60 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/82005 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/83862 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1451 ,  H01L2924/14511 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/19

Abstract: Vertically stacked system in package structures are described. A package includes a first level (125) molding (122) and fan out structure (130), a third level (185) molding (182) and fan out structure (190) and a second level (155) molding (152) and fan out structure (160) between the first and third levels (125, 185). The first level (125) molding (122) and fan out structure (130) includes a first level die (110), the second level (155) molding (152) and fan out structure (160) includes back-to-back facing dies (142), with a front surface of each die (142) bonded to a redistribution layer (130, 160), and the third level (185) molding (182) includes a third level die (172). A plurality of first level molding dies (110) may be used. The first level die (110) may be a volatile memory die, the second level dies (142) may be non-volatile memory dies and the third level die (172) may be an active die. In a method of forming the vertical stack system in package, a carrier substrate may be used and later removed.

Abstract translation: 描述了包装结构中的垂直堆叠系统。 包装包括第一级（125）模制件（122）和扇出结构（130），第三级（185）模制件（182）和扇出结构（190）和第二级（155）模制件（152）和 在第一和第三级（125,185）之间的扇出结构（160）。 第一级（125）模制（122）和扇出结构（130）包括第一级模具（110），第二级（155）模制件（152）和扇出结构（160）包括背对背 模具（142），其中每个模具（142）的前表面结合到再分布层（130,160），并且第三级（185）模制件（182）包括第三级模具（172）。 可以使用多个第一级成型模具（110）。 第一级管芯（110）可以是易失性存储器管芯，第二级管芯（142）可以是非易失性存储器管芯，并且第三级管芯（172）可以是有源管芯。 在封装中形成垂直堆叠系统的方法中，可以使用载体衬底并随后去除。