公开(公告)号：WO1997039479A1

公开(公告)日：1997-10-23

申请号：PCT/US1997002502

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BRENNAN, William, S. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W.

IPC: H01L21/3105

CPC classification number: H01L21/76819 ,  H01L21/31055 ,  H01L21/76229

Abstract: An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of field dielectric having an upper surface substantially coplanar with each other and with adjacent silicon mesa upper surfaces. The isolation process is thereby a planarization process used with the shallow trench technique, wherein etch-enhancing ions are forwarded into the fill dielectric at upper elevational regions of that dielectric. When subjected to a subsequent etchant, the dopants cause the higher elevational regions to be removed at a faster rate than the lower elevational regions. Thus, selective placement of dopants and etch removal pre-conditions the fill dielectric upper surface to a more planar surface globally across the entire wafer. After etch removal predominantly at the higher elevational regions, the remaining fill dielectric upper surface is removed to a level commensurate with the upper surface of silicon mesas thereby producing separate field dielectrics interposed between silicon mesas. The field dielectrics, regardless of their lateral area, each have a substantially planar upper surface at or slightly below the adjoining silicon mesas. By producing planar field dielectric upper surfaces, various problems of non-planarity are removed from the thin films which are thereafter formed on the field dielectrics or between the field dielectrics and silicon mesas.

Abstract translation: 提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。 隔离过程导致间隔开的多个场电介质，其具有彼此基本上共面的上表面和相邻的硅台面上表面。 因此，隔离过程是与浅沟槽技术一起使用的平坦化工艺，其中将蚀刻增强离子转移到该电介质的上部高度区域的填充电介质中。 当经受后续蚀刻剂时，掺杂剂导致以比较低的高度区域更快的速率去除较高的高度区域。 因此，掺杂剂的选择性放置和蚀刻去除预先将填充电介质上表面全局地横跨整个晶片进行预处理。 在主要在较高的高度区域进行蚀刻去除之后，剩余的填充电介质上表面被去除到与硅台面的上表面相当的水平，从而产生介于硅台面之间的单独的场电介质。 场电介质，无论它们的横向面积如何，每个在相邻的硅台面处或稍低于相邻的硅台面处都具有基本平坦的上表面。 通过产生平面场电介质上表面，从形成在场电介质上或在场电介质和硅台面之间的薄膜中去除了非平面性的各种问题。

公开(公告)号：WO1998025183A1

公开(公告)日：1998-06-11

申请号：PCT/US1997023139

申请日：1997-12-04

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  MOORE, Bradley, T. ,  DAWSON, Robert ,  FULFORD, H., Jim ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  MICHAEL, Mark, W. ,  WRISTERS, Derick, J.

IPC: G03F07/20

CPC classification number: G03F7/70058 ,  G03F7/70591 ,  G03F7/70891

Abstract: A method of inspecting a lens (16) includes projecting a first amount of radiation through a first test pattern (42, 44) and the lens to provide a first lens error associated with a first heating of the lens, projecting a second amount of radiation through a second test pattern (52, 54) and the lens to provide a second lens error associated with a second heating of the lens, and using the first and second lens errors to provide image displacement data that varies as a function of heating the lens. In this manner, corrections can be made for localized lens heating that is unique to a given reticle. The method is well-suited for photolithographic systems such as step and repeat systems.

Abstract translation: 检查透镜（16）的方法包括：通过第一测试图案（42,44）和透镜投射第一量的辐射，以提供与透镜的第一加热相关联的第一透镜误差，投射第二量的辐射 通过第二测试图案（52,54）和透镜提供与透镜的第二加热相关联的第二透镜误差，并且使用第一和第二透镜误差来提供作为加热透镜的函数而变化的图像位移数据 。 以这种方式，可以对给定掩模版特有的局部透镜加热进行校正。 该方法非常适合于光刻系统，如步进和重复系统。

公开(公告)号：WO1998010470A1

公开(公告)日：1998-03-12

申请号：PCT/US1997015505

申请日：1997-09-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L29/78

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.

Abstract translation: 公开了一种包括轻掺杂和重掺杂漏极区域和超重掺杂源极区域的非对称IGFET。 优选地，轻掺杂漏极区域和超重掺杂源极区域提供通道结。 制造IGFET的方法包括提供半导体衬底，在衬底上形成具有第一和第二相对侧壁的栅极，施加第一离子注入以将轻掺杂的源极和漏极区域注入到衬底中，施加第二离子注入以基本上转换 将所有轻掺杂源区域全部掺入重掺杂源区，而不掺杂轻掺杂漏极区，形成与第二侧壁相邻的漏极侧隔离层，以及施加第三离子注入以将重掺杂源区转换成超掺杂源区， 并且将漏极侧间隔物外部的轻掺杂漏极区域的一部分转换为重掺杂漏极区域，而不将漏极侧间隔物下方的轻掺杂漏极区域的一部分掺杂。 有利地，IGFET具有低的源极 - 漏极串联电阻并且降低热载流子效应。

公开(公告)号：WO1998004892A1

公开(公告)日：1998-02-05

申请号：PCT/US1997005113

申请日：1997-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  HAUSE, Frederick, N. ,  MAY, Charles, E.

IPC: G01J05/60

CPC classification number: G01J5/601 ,  G01J5/041 ,  G01J5/60

Abstract: A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.

Abstract translation: 使用宽带高温计来检测与单色仪相关联的RTA系统中的半导体晶片的温度，以消除半导体晶片的背面特性。 快速热退火（RTA）系统包括快速热退火（RTA）室，布置在RTA室附近的加热灯，用于加热到RTA室内部，宽带高温计设置在RTA室附近并被引导 测量RTA室的内部，以及连接到宽带高温计的光栅单色仪。

公开(公告)号：WO1998003994A1

公开(公告)日：1998-01-29

申请号：PCT/US1997009452

申请日：1997-05-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  MICHAEL, Mark, W. ,  BRENNAN, William, S.

IPC: H01L21/768

CPC classification number: H01L23/5222 ,  H01L21/76816 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multilevel interconnect structure (10) is provided. The multilevel interconnect structure includes at least three levels of interconnect (conductors) formed according to one exemplary embodiment. Two of the three levels (12) of conductors are staggered from each other (16) in separate vertical and horizontal planes. A third conductor (16) is advantageously spaced a lateral distance between at least a portion of two second conductors (26). The third conductor is also placed in an elevational level below or possibly above the second conductor so as to reduce the capacitive coupling therebetween. By staggering the second and third conductors, high density interconnect can be achieved with minimal propagation delay and cross coupling.

Abstract translation: 提供了多层互连结构（10）。 多层互连结构包括根据一个示例性实施例形成的至少三层互连（导体）。 导体的三个层（12）中的两个在单独的垂直和水平平面中彼此交错（16）。 第三导体（16）有利地在两个第二导体（26）的至少一部分之间隔开横向距离。 第三导体也被放置在第二导体的下方或可能的第二导体的上方，以减小它们之间的电容耦合。 通过交错第二和第三导体，可以以最小的传播延迟和交叉耦合实现高密度互连。

公开(公告)号：WO1997047038A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002329

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  MICHAEL, Mark, W. ,  BANDYOPADHYAY, Basab ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N. ,  BRENNAN, William, S.

IPC: H01L23/522

CPC classification number: H01L23/5222 ,  H01L23/5226 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors (14, 16), wherein conductors (14) on one level are staggered with respect to conductors (11) on another level. Accordingly, a space (32, 34) between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics (24) which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overal intrinsic stress of the resulting intralevel and interlevel dielectric structure.

Abstract translation: 提供了一种改进的多级互连结构。 互连结构包括几层导体（14,16），其中一个层上的导体（14）相对于另一层上的导体（11）交错。 因此，一个级别的导体之间的空间（32,34）直接在另一个水平的导体的正上方或正下方。 交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。 此外，层间和层间介质结构包括存在于临界间隔区域中的最佳放置的低K电介质（24），以最小化电容耦合和传播延迟问题。 根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。 封盖电介质进一步最小化所得到的层间和层间电介质结构的内在应力。

公开(公告)号：WO1997047034A1

公开(公告)日：1997-12-11

申请号：PCT/US1997002503

申请日：1997-02-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  BRENNAN, William, S. ,  DAWSON, Robert ,  FULFORD, H., Jim, Jr. ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  MICHAEL, Mark, W.

IPC: H01L21/768

CPC classification number: H01L21/76877

Abstract: A multilevel interconnect structure is provided. The multilevel interconnect structure includes two, three or more levels of conductors formed according to at least two exemplary embodiments. According to one embodiment, the contact structure which links conductors (12) on one level to an underlying level is formed by a single via etch step followed by a fill step separate from a fill step used in filling the via. In this embodiment, the via (24) is filled with a conductive material (30) which forms a plug separate from the material (14) used in forming the interconnect. In another exemplary embodiment, the step used in filling the via can be the same as that used in forming the interconnect. In either instance, a via is formed through a first dielectric (22) to underlying conductors. A second dielectric (36) is patterned upon the first dielectric and serves to laterally bound the fill material used in producing the overlying interconnect. Regardless of the process sequence chosen, the interlevel dielectric structure (36) is left substantially planar in readiness for subsequent interconnect levels dielectrically deposited thereon.

Abstract translation: 提供了多层互连结构。 多层互连结构包括根据至少两个示例性实施例形成的两层，三层或更多级的导体。 根据一个实施例，通过单个通孔蚀刻步骤形成将一个层上的导体（12）连接到下面的层的接触结构，随后是与用于填充通孔的填充步骤分离的填充步骤。 在该实施例中，通孔（24）填充有形成与用于形成互连件的材料（14）分开的插头的导电材料（30）。 在另一个示例性实施例中，用于填充通孔的步骤可以与在形成互连中使用的步骤相同。 在任一情况下，通过第一电介质（22）到底层导体形成通孔。 第二电介质（36）在第一电介质上被图案化，并且用于横向地限制用于制造上覆互连的填充材料。 不管所选择的工艺顺序如何，层间电介质结构（36）保持基本平坦，以便随后在其上介电沉积的互连层。

公开(公告)号：WO1997041592A1

公开(公告)日：1997-11-06

申请号：PCT/US1996020485

申请日：1996-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： ADVANCED MICRO DEVICES, INC. ,  DAWSON, Robert ,  HAUSE, Fred, N. ,  BANDYOPADHYAY, Basab ,  MICHAEL, Mark, W. ,  FULFORD, H., Jim ,  BRENNAN, William, S.

IPC: H01L21/316

CPC classification number: H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A low permittivity interlevel structure comprising a dielectric formed on the topography of a semiconductor substrate. The dielectric comprises a lower region proximal to the semiconductor substrate, an intermediate region comprised of an oxide into which fluorine is incorporated in an atomic concentration of approximately four to ten percent, and an upper region. A method of forming the dielectric structure includes forming a first interconnect level on a substrate. A first dielectric layer, preferably a CVD oxide, is formed on the topography defined by the first interconnect and the substrate. A second dielectric layer, having a dielectric constant lower than the first dielectric layer, is then formed on the first dielectric layer. A third dielectric layer is formed on the second dielectric layer. The second dielectric layer is preferably formed in a CVD chamber from a silane or TEOS source and a fluorinating material such as SiF4.

Abstract translation: 包括在半导体衬底的形貌上形成的电介质的低介电常数层间结构。 电介质包括靠近半导体衬底的下部区域，由以约4％至10％的原子浓度掺入氟的氧化物构成的中间区域和上部区域。 形成电介质结构的方法包括在衬底上形成第一互连电平。 在由第一互连和衬底限定的形貌上形成第一电介质层，优选CVD氧化物。 然后在第一介电层上形成具有低于第一介电层的介电常数的第二电介质层。 在第二电介质层上形成第三电介质层。 第二电介质层优选地由硅烷或TEOS源形成在CVD室中，并且氟化材料例如SiF 4。

公开(公告)号：EP1070348A1

公开(公告)日：2001-01-24

申请号：EP98955236.9

申请日：1998-11-02

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： DAWSON, Robert ,  GARDNER, Mark, I. ,  HAUSE, Frederick, N. ,  FULFORD, H., Jim, Jr. ,  MICHAEL, Mark, W. ,  MOORE, Bradley, T. ,  WRISTERS, Derick, J.

IPC: H01L21/768

CPC classification number: H01L21/76895

Abstract: A local interconnect (LI) structure (112) is formed by forming a silicide layer (60, 50) in selected regions of a semiconductor structure then depositing an essentially uniform layer (110) of transition or refractory metal overlying the semiconductor structure. The metal local interconnect (112) is deposited without forming an intermediate insulating layer between the silicide (60, 50) and metal layers (110) to define contact openings or vias. In some embodiments, titanium is a suitable metal for formation of the local interconnect (112). Suitable selected regions (60) for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions (50). The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etch-stop layer (100) is desired for the patterning of the metal film, a first optional insulating layer (100) is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.

公开(公告)号：EP0938752A1

公开(公告)日：1999-09-01

申请号：EP97939764.0

申请日：1997-09-03

Applicant: Advanced Micro Devices, Inc.

Inventor： KADOSH, Daniel ,  GARDNER, Mark, I. ,  DAWSON, Robert

IPC: H01L21 ,  H01L29

CPC classification number: H01L29/66659 ,  H01L29/665 ,  H01L29/7835

Abstract: An asymmetrical IGFET including a lightly and heavily doped drain regions and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and ultra-heavily doped source region provide channel junctions. A method of making the IGFET includes providing a semiconductor substrate, forming a gate with first and second opposing sidewalls over the substrate, applying a first ion implantation to implant lightly doped source and drain regions into the substrate, applying a second ion implantation to convert substantially all of the lightly doped source region into a heavily doped source region without doping the lightly doped drain region, forming a drain-side spacer adjacent to the second sidewall, and applying a third ion implantation to convert the heavily doped source region into an ultra-heavily doped source region and to convert a portion of the lightly doped drain region outside the drain-side spacer into a heavily doped drain region without doping a portion of the lightly doped drain region beneath the drain-side spacer. Advantageously, the IGFET has low source-drain series resistance and reduces hot carrier effects.