公开(公告)号：US20130181346A1

公开(公告)日：2013-07-18

申请号：US13743844

申请日：2013-01-17

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Yie-Chuan Chiu ,  Lung-Hua Ho

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/034 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11472 ,  H01L2224/1182 ,  H01L2224/11906 ,  H01L2224/13147 ,  H01L2224/13562 ,  H01L2224/13564 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01029 ,  H01L2924/01028 ,  H01L2224/05552

Abstract: A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots, forming a plurality of bottom coverage layers at the opening slots, proceeding a heat procedure, forming a plurality of external coverage layers to make each of the external coverage layers connect with each of the bottom coverage layers, wherein said external coverage layer and said bottom coverage layer form a wrap layer and completely surround the copper bump, forming a plurality of connective layers on the external coverage layers, removing the photoresist layer, removing the second areas and enabling each of the first areas to form an under bump metallurgy layer.

Abstract translation: 凸起工艺包括提供硅衬底，在硅衬底上形成含钛金属层，其中含钛金属层包括多个第一区域和多个第二区域，在含钛金属层上形成光致抗蚀剂层 金属层，图案化光致抗蚀剂层以形成多个开口槽，在开口槽处形成多个底部覆盖层，进行热过程，形成多个外部覆盖层，以使每个外部覆盖层与每个 的底部覆盖层，其中所述外部覆盖层和所述底部覆盖层形成包裹层并且完全围绕铜凸块，在外部覆盖层上形成多个连接层，去除光致抗蚀剂层，去除第二区域并使能 每个第一区域形成凸块下的冶金层。

公开(公告)号：US12224183B2

公开(公告)日：2025-02-11

申请号：US17896171

申请日：2022-08-26

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Shrane-Ning Jenq ,  Wen-Cheng Hsu ,  Chen-Yu Wang ,  Chih-Ming Kuo ,  Chwan-Tyaw Chen ,  Lung-Hua Ho

IPC: H01L21/48 ,  C23C18/54 ,  C23C28/02 ,  C25D7/12 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/498 ,  H01L23/00

Abstract: A package including a first carrier, a seed layer, wires, a die and a molding material is provided. The first carrier is removed to expose the seed layer after disposing a second carrier on the molding material, then the seed layer is removed to expose the wires, and a gold layer is deposited on each of the wires by immersion gold plating, finally a semiconductor device is obtained. The gold layer is provided to protect the wires from oxidation and improve solder joint reliability.

公开(公告)号：US20230378044A1

公开(公告)日：2023-11-23

申请号：US18109337

申请日：2023-02-14

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Lung-Hua Ho ,  Chih-Ming Kuo ,  Chun-Ting Kuo ,  Yu-Hui Hu ,  Chih-Hao Chiang ,  Chen-Yu Wang ,  Kung-An Lin ,  Pai-Sheng Cheng

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/13014 ,  H01L2224/16227

Abstract: A flip-chip bonding structure includes a substrate and a chip. A lead of the substrate includes a body, a hollow opening, a bonding island and at least one connecting bridge. The hollow opening is in the body and surrounded by the body. The bonding island is located in the hollow opening such that there is a hollow space in the hollow opening and located between the body and the bonding island. The connecting bridge is located in the hollow space to connect the body and the bonding island. A bump of the chip is bonded to the bonding island by a solder. The solder is restricted on the bonding island and separated from the body by the hollow space so as to avoid the solder from overflowing to the body and avoid the chip from shifting.

公开(公告)号：US08772644B2

公开(公告)日：2014-07-08

申请号：US13644709

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu

IPC: H05K1/16

CPC classification number: H01L23/5223 ,  H01G4/01 ,  H01L28/86 ,  H01L2924/0002 ,  H05K1/162 ,  H01L2924/00

Abstract: A carrier with three-dimensional capacitor includes a substrate and a three-dimensional capacitor, wherein the substrate comprises a trace layer having a first terminal and a second terminal. The three-dimensional capacitor is integrally formed as one piece with the trace layer. The three-dimensional capacitor and the trace layer are made of same material. The three-dimensional capacitor comprises a first capacitance portion and a second capacitance portion, the first capacitance portion comprises a first section, a second section and a first passage, the second capacitance portion is formed at the first passage. The second capacitance portion comprises a third section, a fourth section and a second passage communicated with the first passage. The first capacitance portion is located at the second passage, a first end of the first capacitance portion connects to the first terminal, and a third end of the second capacitance portion connects to the second terminal.

Abstract translation: 具有三维电容器的载体包括基板和三维电容器，其中所述基板包括具有第一端子和第二端子的迹线层。 三维电容器与轨迹层一体形成。 三维电容器和迹线层由相同的材料制成。 三维电容器包括第一电容部分和第二电容部分，第一电容部分包括第一部分，第二部分和第一通道，第二电容部分形成在第一通道处。 第二电容部分包括与第一通道连通的第三部分，第四部分和第二通道。 第一电容部分位于第二通道处，第一电容部分的第一端连接到第一端子，第二电容部分的第三端连接到第二端子。

公开(公告)号：US20130027172A1

公开(公告)日：2013-01-31

申请号：US13644964

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00

CPC classification number: H01F5/00 ,  H01F5/003 ,  H05K1/165 ,  H05K3/465 ,  H05K2201/097 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49155

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract translation: 一种制造具有三维电感器的载体的方法包括以下步骤：提供具有保护层的衬底; 在保护层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成第二开口和多个布置槽; 在第二开口中形成第一金属层并设置槽; 去除第一光致抗蚀剂层; 在所述保护层上形成第一介电层; 在所述第一介电层上形成第二光致抗蚀剂层; 图案化第二光致抗蚀剂层以形成多个槽; 在槽中形成第二金属层以形成多个感应部分; 去除所述第二光致抗蚀剂层; 在所述第一电介质层上形成第二电介质层; 在所述第二介电层上形成第三光致抗蚀剂层; 图案化第三光致抗蚀剂层以形成多个狭缝; 以及在槽中形成第三金属层。

公开(公告)号：US09059260B2

公开(公告)日：2015-06-16

申请号：US14164628

申请日：2014-01-27

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Shih-Chieh Chang ,  Chia-Yeh Huang ,  Chin-Tang Hsieh

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/76885 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

Abstract translation: 半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部， 突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖 突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。

公开(公告)号：US08963675B2

公开(公告)日：2015-02-24

申请号：US13644964

申请日：2012-10-04

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00 ,  H01F27/28 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01F5/00 ,  H01F5/003 ,  H05K1/165 ,  H05K3/465 ,  H05K2201/097 ,  Y10T29/4902 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49155

Abstract: A method for fabricating a carrier with a three-dimensional inductor comprises the steps of providing a substrate having a protective layer; forming a first photoresist layer on the protective layer; patterning the first photoresist layer to form a second opening and a plurality of disposing slots; forming a first metal layer in second opening and disposing slots; removing the first photoresist layer; forming a first dielectric layer on the protective layer; forming a second photoresist layer on the first dielectric layer; patterning the second photoresist layer to form a plurality of slots; forming a second metal layer in slots to form a plurality of inductive portions; removing the second photoresist layer; forming a second dielectric layer on the first dielectric layer; forming a third photoresist layer on the second dielectric layer; patterning the third photoresist layer to form a plurality of slots; and forming a third metal layer in slots.

Abstract translation: 一种制造具有三维电感器的载体的方法包括以下步骤：提供具有保护层的衬底; 在保护层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层以形成第二开口和多个布置槽; 在第二开口中形成第一金属层并设置槽; 去除第一光致抗蚀剂层; 在所述保护层上形成第一介电层; 在所述第一介电层上形成第二光致抗蚀剂层; 图案化第二光致抗蚀剂层以形成多个槽; 在槽中形成第二金属层以形成多个感应部分; 去除所述第二光致抗蚀剂层; 在所述第一电介质层上形成第二电介质层; 在所述第二介电层上形成第三光致抗蚀剂层; 图案化第三光致抗蚀剂层以形成多个狭缝; 以及在槽中形成第三金属层。

公开(公告)号：US08841767B2

公开(公告)日：2014-09-23

申请号：US13852663

申请日：2013-03-28

Applicant: Chipbond Technology Corporation

Inventor： Chin-Tang Hsieh ,  Chih-Ming Kuo

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05541 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05557 ,  H01L2224/05565 ,  H01L2224/05567 ,  H01L2224/05578 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05687 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/13687 ,  H01L2924/00014 ,  H01L2924/301 ,  H01L2924/384 ,  Y10T428/12396 ,  H01L2924/00012 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/058 ,  H01L2224/05552

Abstract: A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.

Abstract translation: 凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分 连接层可以覆盖那些外围壁以防止电离现象。

公开(公告)号：US20130127578A1

公开(公告)日：2013-05-23

申请号：US13739210

申请日：2013-01-11

Applicant: Chipbond Technology Corporation

Inventor： Chih-Ming Kuo ,  You-Ming Hsu

IPC: H01F5/00

CPC classification number: H01L23/48 ,  H01F5/00 ,  H01F5/003 ,  H01F17/0033 ,  H01F41/046 ,  H01L28/10

Abstract: A method for fabricating a inductor carrier comprises the steps of providing a substrate with a protective layer; forming a first photoresist layer on protective layer; patterning the first photoresist layer to form a first opening and first apertures; forming a first metal layer within first opening and first apertures; removing the first photoresist layer; forming a first dielectric layer on protective layer; forming a second photoresist layer on first dielectric layer; patterning the second photoresist layer to form a second aperture and a plurality of third apertures; forming a second metal layer within second aperture and third apertures; removing the second photoresist layer; forming a second dielectric layer on first dielectric layer; forming a third photoresist layer on second dielectric layer; patterning the third photoresist layer to form a fifth aperture and sixth apertures; forming a third metal layer within fifth aperture and sixth apertures.

公开(公告)号：US11651974B2

公开(公告)日：2023-05-16

申请号：US17161818

申请日：2021-01-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  You-Ming Hsu ,  Fei-Jain Wu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/562

Abstract: A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.