公开(公告)号：AU5169193A

公开(公告)日：1994-04-26

申请号：AU5169193

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DALE J ,  LANDRY JOHN A

IPC: G06F13/24

Abstract: A computer system includes a filter at an interrupt request input for a microprocessor system. The interrupt signal filter suppresses any positive pulse that is shorter than 9 cycles of the host clock. Only signals that are asserted for at least 17 HCLK cycles are guaranteed passage to the interrupt controller to assert the interrupt request. In addition, any negative pulse on the IRQ signal is latched and extended for at least 9 cycles of the host clock. The filter thus suppresses noise to prevent unnecessary interrupts, and provides for enhanced detection of negative levels and rising edges for negative-going interrupt request signals.

公开(公告)号：DE69427421T2

公开(公告)日：2001-11-15

申请号：DE69427421

申请日：1994-03-22

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  SANTELER PAUL A ,  THOME GARY W ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：CA2145404C

公开(公告)日：1999-04-06

申请号：CA2145404

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A

IPC: G06F11/00 ,  G06F11/22 ,  G06F15/177 ,  G06F9/00

Abstract: A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPUO. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot O (CPU PO) are initially placed in an inactive sleep state. The microprocessor in physical location O performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPUO (CPU LO). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU PO is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU LO functions.

公开(公告)号：CA2119174A1

公开(公告)日：1994-09-23

申请号：CA2119174

申请日：1994-03-16

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  THOME GARY W ,  SANTELER PAUL A ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F12/02

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：AU5441494A

公开(公告)日：1994-04-26

申请号：AU5441494

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A

IPC: G06F11/00 ,  G06F11/22 ,  G06F15/177 ,  G06F15/16

Abstract: A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

公开(公告)号：AU5297093A

公开(公告)日：1994-04-26

申请号：AU5297093

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： CULLEY PAUL R ,  LANDRY JOHN A ,  MAYER DALE J ,  WANNER CHRISTOPHER C ,  MCSWAIN GUY E

IPC: G06F13/24 ,  G06F13/32 ,  G06F15/80

Abstract: An arrangement of direct memory access (DMA), interrupt and timer functions in a multiprocessor computer system to allow symmetrical processing. Several functions which are considered common to all of the CPUs and those which are conveniently accessed through an expansion bus remain in a central system peripheral chip coupled to the expansion bus. These central functions include the primary portions of the DMA controller and arbitration circuitry to control access of the expansion bus. A distributed peripheral, including a programmable interrupt controller, multiprocessor interrupt logic, nonmaskable interrupt logic, local DMA logic and timer functions, is provided locally for each CPU. A bus is provided between the central and distributed peripherals to allow the central peripheral to broadcast information to the CPUs, and to provide local information from the distributed chip to the central peripheral when the local CPU is programming or accessing functions in the central peripheral.

公开(公告)号：CA2145404A1

公开(公告)日：1994-04-14

申请号：CA2145404

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A

IPC: G06F11/00 ,  G06F11/22 ,  G06F15/177 ,  G06F9/00

Abstract: A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

公开(公告)号：CA2028551A1

公开(公告)日：1991-05-04

申请号：CA2028551

申请日：1990-10-25

Applicant: COMPAQ COMPUTER CORP

Inventor： THAYER JOHN S ,  MAYER DALE J ,  IZQUIERDO JAVIER F ,  CULLEY PAUL R ,  LANDRY JOHN A

IPC: G06F12/06 ,  G06F12/00

Abstract: DATA DESTINATION FACILITY A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided.

公开(公告)号：CA2027819A1

公开(公告)日：1991-05-04

申请号：CA2027819

申请日：1990-10-17

Applicant: COMPAQ COMPUTER CORP

Inventor： MELO MARIA L ,  LANDRY JOHN A ,  CULLEY PAUL R ,  GOODRUM ALAN L

IPC: G06F13/26 ,  G06F13/362 ,  G06F13/40 ,  G06F13/42 ,  G06F1/04 ,  G06F1/14

Abstract: A design which allows for the addition of a programmable delay between back-to-back I/O cycles in a computer system is shown. The addition of the programmable delay allows utilization of the minimum amount of delay between back-to-back I/O cycles that is required to maintain compatibility between the computer system and the particular 8-bit or 16-bit I/O devices being used. A programmed value reflecting a particular length of delay is used to generate a signal that is pulse position modulated with this length of delay. The pulse position modulated signal is used in conjunction with a counter that counts out a predetermined length of delay dependent on the particular I/O cycle that has just been completed. The pulse position modulated signal terminates the delay being provided by the counter when the programmed length of delay has expired.