公开(公告)号：EP0621539B1

公开(公告)日：2001-08-29

申请号：EP94301988.5

申请日：1994-03-21

Applicant: Compaq Computer Corporation

Inventor： Thome, Gary W. ,  Collins, Michael J.

IPC: G06F13/42 ,  G11C8/00 ,  G06F13/28

CPC classification number: G11C8/18 ,  G06F13/4243 ,  G11C7/1018 ,  G11C7/22

公开(公告)号：EP0707268A3

公开(公告)日：1996-07-31

申请号：EP95307349.1

申请日：1995-10-13

Applicant: Compaq Computer Corporation

Inventor： Stevens, Jeffrey C. ,  Thome, Gary W. ,  Larson, John E. ,  Collins, Michael J. ,  Moriarty, Michael

IPC: G06F12/06

CPC classification number: G06F13/4243 ,  G06F13/1689 ,  G06F13/1694

Abstract: A memory controller for a computer system provides a series of queues between the processor and a PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI-to-memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI-to-memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI-to-memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional dynamic random access memory cycle which are used to control state machine operations.

公开(公告)号：EP0617367A2

公开(公告)日：1994-09-28

申请号：EP94302036.2

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Ayash, Basem Abu ,  Thome, Gary W.

IPC: G06F13/24

CPC classification number: G06F9/4812 ,  G06F9/463 ,  G06F12/02 ,  G06F13/24

Abstract: A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Abstract translation: 当计算机处于系统管理模式时，用于计算机的系统管理模式地址校正系统在地址总线上提供正确的地址值。 通常，微处理器地址输出的位20可以通过声明FORCE A20信号来屏蔽。 计算机系统还以系统管理模式运行，这要求所有地址位可用于正确访问系统管理中断向量。 当计算机处于系统管理模式时，计算机的微处理器断言系统管理中断激活（SMIACT *）信号。 该信号被提供给也接收FORCE A20信号的电路。 当SMIACT信号被去激活时，控制电路将真实的FORCE A20信号提供给计算机系统。 发生SMI时，SMIACT信号被激活，而FORCE A20信号被禁止。 结果，微处理器产生的地址在地址总线上被断言。

公开(公告)号：EP0617365A1

公开(公告)日：1994-09-28

申请号：EP94302014.9

申请日：1994-03-22

Applicant: Compaq Computer Corporation

Inventor： Landry, John A. ,  Santeler, Paul A. ,  Thome, Gary W. ,  Bonella, Randy M. ,  Collins, Michael J.

IPC: G06F13/16

CPC classification number: G06F13/1615

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

Abstract translation: 一个内存控制器，最大限度地利用任何处理器流水线并同时运行大量的周期。 存储器控制器可以利用不同的速度存储器件并以其期望的最佳速度运行每个存储器件。 这些功能由多个简单的相互依赖的状态机执行，每个状态机负责整个操作的一小部分。 当每个状态机达到完成其功能时，它通知相关状态机现在可以继续进行，并继续等待下一个启动或继续指示。 下一台状态机以类似的方式运行。 负责一个周期的较早部分的状态机在下一个周期中开始执行任务，然后在负责周期的后期部分的状态机完成任务之前。 存储器控制器在逻辑上组织为三个主要块，前端块，存储块和主机块，每个都负责与其相关总线和组件的交互，并与各种其他块进行交互。 存储器控制器使用不同的速度存储器件，例如60ns和80ns，各个存储器件以其完全设计的速率工作。 存储器的速度是针对每个128K字节的存储器存储的，并且当发生存储器周期以重定向状态机时，使用该存储器的速度，从而实现存储器件的定时改变。