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    SEMICONDUCTOR DEVICE FOR RESISTANCE STRUCTURES IN HIGH-DENSITY INTEGRATED CIRCUITS AND METHOD FOR MAKING IT
    14.
    发明专利
    SEMICONDUCTOR DEVICE FOR RESISTANCE STRUCTURES IN HIGH-DENSITY INTEGRATED CIRCUITS AND METHOD FOR MAKING IT 未知

    公开(公告)号：DE2861533D1

    公开(公告)日：1982-02-25

    申请号：DE2861533

    申请日：1978-09-29

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CHANG AUGUSTINE WEI-CHUN

    IPC: H01L27/04 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L21/82 ,  H01L21/822 ,  H01L27/08 ,  H01L27/118 ,  H01L29/73 ,  H01L29/8605 ,  H01L29/861 ,  H01L21/70 ,  H01L29/86

    Abstract: A high sheet resistance structure for high density integrated circuits and the method for manufacturing such structure is given. The structure includes a silicon region separated from other silicon regions by a dielectric barrier surrounding the region. A resistor of a first conductivity, for example, N type, encompasses substantially the surface of the silicon region. Electrical contacts are made to the resistor. A region highly doped of a second conductivity, for example, P-type, is located below a portion of the resistor region. This region of second conductivity is connected to the surface. Electrical contacts are made to this varied region for biasing purposes. A second region within the same isolated silicon region may be used as a resistor. This region is located below the buried region of second conductivity. Alternatively, the described resistor regions can be connected as transistors. This allows the formation of a standard masterslice which can be personalized at a late stage in the manufacturing to either resistors or transistors in all or a portion of the standard regions.

    METHOD FOR FABRICATING VERTICAL NPN AND LATERAL PNP TRANSISTORS IN THE SAME SEMICONDUCTOR BODY
    15.
    发明专利
    METHOD FOR FABRICATING VERTICAL NPN AND LATERAL PNP TRANSISTORS IN THE SAME SEMICONDUCTOR BODY 未知

    公开(公告)号：DE3466832D1

    公开(公告)日：1987-11-19

    申请号：DE3466832

    申请日：1984-06-08

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR GUNDAPPA ,  RISEMAN JACOB ,  TSANG PAUL JAMIN

    IPC: H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8224 ,  H01L27/082 ,  H01L29/73 ,  H01L29/732 ,  H01L29/735 ,  H01L21/72 ,  H01L29/72 ,  H01L27/08

    Abstract: The lateral transistor is described which has both its base width and the emitter region of the transistor minimized. This minimization of the elements of the lateral transistor gives high performance. The lateral transistor which may be typically PNP transistor is formed in a monocrystalline semiconductor body having a buried N+ region within the body. A P type emitter region is located in the body. An N type base region is located around the side periphery of the emitter region. A P type collector region is located in the body surrounding the periphery of the base region. A first P+ polycrystalline silicon layer acting as an emitter contact for the emitter region is in physical and electrical contact with the emitter region and acts as its electrical contact. A second P+ polycrystalline silicon layer is located on the surface of the body to make physical and electrical contact with the collector region. A vertical insulator layer on the edge of the second polycrystalline silicon layer isolates the two polycrystalline silicon layers from one another. The N base region at its surface is located underneath the width of the vertical insulator layer. An N+ reach-through region extending from the surface of the body to the buried N+ region acts as an electrical contact through the N+ buried layer to the base region. The width of the vertical insulator has a width which is equal to the desired base width of the lateral PNP transistor plus lateral diffusions of the collector and emitter junctions of the lateral PNP. The preferred structure is to have the emitter formed around the periphery of a channel or groove which has at its base a insulating layer such as silicon dioxide. The parasitic transistor is almost totally eliminated by this buried oxide isolation.

    SEMICONDUCTOR DEVICES
    19.
    发明专利
    SEMICONDUCTOR DEVICES 未知

    公开(公告)号：GB1270498A

    公开(公告)日：1972-04-12

    申请号：GB5991170

    申请日：1970-12-17

    Applicant: IBM

    Inventor： ANANTHA NARASIPUR GUNDAPPA

    IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/08

    Abstract: 1,270,498. Semi-conductor devices. INTERNATIONAL BUSINESS MACHINES CORP. 17 Dec., 1970 [30 Dec., 1969], No. 59911/70. Heading H1K. A semi-conductor device comprises a P-type region, a contiguous N-type region of high resistivity, a metallic layer forming a Schottky barrier junction with the N region, and a further, low resistivity, region in ohmic contact with the other side of the metallic layer. The P- region, 109, forms the emitter region of a transistor, the N region, 106, the base, having a resistivity of from 0À07 to 5À0 # cms., and the metal layer 104, the collector. The metallic layer is supported by the further, P, region 103 of less than 0À02 # cms. resistivity, which provides a low resistivity path, via the reach-through region 108, to the collector electrode 117. The metallic layer may consist of a deposited layerof platinum or molybdenum heat treated with the silicon body to form a silicide. The base region 106 may be epitaxially deposited, and regions 103 and 109 formed by diffusion. Arsenic and phosphorus may be dopants, the body may alternatively be of germanium. A plurality of devices may be formed in a single body which is subsequently divided. In an alternative embodiment, the metal layer is deposited on an N+ layer and surrounded laterally by P + regions to reduce edge effects. Contact is made to the N + layer on the underside of the wafer.

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