公开(公告)号：DE3854616D1

公开(公告)日：1995-11-30

申请号：DE3854616

申请日：1988-12-12

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  BORDEN TERRY LEE ,  BUTWELL JUSTIN RALPH ,  CLARK CARL EDWARD ,  GANEK ALAN GEORGE ,  LUM JAMES ,  MALL MICHAEL GERARD ,  PAGE DAVID RICHARD ,  PLAMBECK KENNETH ERNST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24 ,  G06F12/02

Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

公开(公告)号：DE69229203D1

公开(公告)日：1999-06-24

申请号：DE69229203

申请日：1992-08-27

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  CARLSON BRENT ALLEN ,  KIM MOON JU ,  MALL MICHAEL GERARD ,  SCALZI CASPER ANTHONY ,  SINHA BHASKAR

IPC: G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06

公开(公告)号：DE69021710D1

公开(公告)日：1995-09-21

申请号：DE69021710

申请日：1990-10-31

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  BROTMAN CHARLES H ,  RYMARCZYK JAMES WALTER

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/10 ,  G06F11/14 ,  G06F11/20 ,  G06F13/00 ,  G06F13/36 ,  G06F15/173

Abstract: A large number of processing elements (604) (e.g. 4096) are interconnected by means of a high bandwidth switch (606). Each processing element (604) includes one or more general purpose microprocessors (1202), a local memory (1210) and a DMA controller (1206) that sends and receives messages through the switch (606) without requiring processor intervention. The switch (606) that connects the processing elements is hierarchical and comprises a network of clusters. Sixtyfour processing elements (604) can be combined to form a cluster and and sixtyfour clusters can be linked by way of a Banyan network. Messages are routed through the switch (606) in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch (606) reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element (604), the processing element (604) corrects the error and retransmits the packet through the switch (606) over a different path. In one embodiment, each processing element can be provided with a hardware accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.

公开(公告)号：MX9205088A

公开(公告)日：1993-03-01

申请号：MX9205088

申请日：1992-09-04

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  CARLSON BRENT ALLEN ,  KIM MOON JU ,  MALL MICHAEL GERARD ,  SCALZI CASPER ANTHONY ,  SINHA BHASKAR NMN

IPC: G06F9/32 ,  G06F9/355 ,  G06F12/02 ,  G06F12/06 ,  G11C5/00

公开(公告)号：BR8900568A

公开(公告)日：1989-10-10

申请号：BR8900568

申请日：1989-02-09

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  BORDEN TERRY LEE ,  BUTWELL JUSTIN RALPH ,  CLARK CARL EDWARD ,  GANEK ALAN GEORGE ,  LUM JAMES ,  MALL MICHAEL GERARD ,  PAGE DAVID RICHARD ,  PLAMBECK KENNETH ERNEST ,  SCALZI CASPER ANTHONY ,  SCHMALZ RICHARD JOHN

IPC: G06F12/08 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14 ,  G06F21/24 ,  G06F9/00

Abstract: A program authorization mechanism for authorizing access to an address space in the main memory of a computer system by a program being run under a multiple address space facility. An access-list entry is associated with each address space, each access-list entry being designated by an access-list-entry token contained in an access register. Each access-list entry includes a private indicator which indicates if the associated address space can be accessed by all programs from this access-list entry or if the associatd address space can only be accessed by an authorized program. For a program to be authorized, an extended authorization index in a control register must match an access-list extended authorization index in the access-list entry, or the extended authorization index value must be authorized in an authority table associated with the address space. An instruction for testing a given extended authorization index for a given access-list-entry is also disclosed.

公开(公告)号：DE3279236D1

公开(公告)日：1988-12-29

申请号：DE3279236

申请日：1982-05-24

Applicant: IBM

Inventor： BAUM RICHARD IRWIN ,  SAKALAY FREDERICK ELIAS

IPC: G06F11/34

Abstract: The disclosure provides a hardware monitor device connectable to a large high speed processor in a uniprocessor or multiprocessor system to correlate software activity to hardware activity by capturing samples of instruction addresses (which are architecturally visible to the software) that cause the occurrence of the monitored activity manifested by electrical signals in processor circuit (e.g. setting of a latch), and recording the instruction addresses with a designation of the monitored event(s), e.g. cache miss. The embodiment samples which instructions are to be captured by selecting one per N number of samplings of a specified event to be monitored. An MP embodiment makes possible the monitoring of software and/or hardware relationships between processors in a multiprocessor by connecting a monitor to each processor being monitored, and interconnecting an event capture signal generated in one processor monitor (master) to control the capture recording means in another processor monitor (slave), so that the recorded information can indicate if the instruction in one processor is responsible for an event occurring in the other processor. A personalization register in each monitor is loaded by a control processor with the identifier of the processor being monitored, the sample count value N, a designation of the particular capturable event which is to control the capture of its causative instruction address, and a designation of other events or conditions whose current state will be indicated as part of the captured data.