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公开(公告)号：IT7927740D0
公开(公告)日：1979-11-30
申请号：IT2774079
申请日：1979-11-30
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOELLING HERMANN , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：FR2406851A1
公开(公告)日：1979-05-18
申请号：FR7828926
申请日：1978-10-02
Applicant: IBM
Inventor： BAZLEN DIETER , BERGER ROLF , BLUM ARNOLD , BOCK DIETRICH W , CHILINSKI HERBERT , GENG HELLMUTH R , HAJDU JOHANN , IRRO FRITZ , NEUBER SIEGFRIED , WILLE UDO
Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.
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公开(公告)号：FR2280934A1
公开(公告)日：1976-02-27
申请号：FR7521458
申请日：1975-07-01
Applicant: IBM
Inventor： BLUM ARNOLD , HAJDU JOHANN , MOHR CLAUD , REICHL LEOPOLD , SONNTA GUNTHER
Abstract: Input/output registers integrated with logic and arithmetic circuits are combined externally of a processor nucleus having only storage registers, instruction decode logic, timing circuitry and arithmetic and logic unit for executing microinstructions whereby the use of the input/output registers is determined by microprogram code and by time control to either selectively execute all adapter and interface communication and control functions for input and output devices or to selectively be switched into the data flow of the processor nucleus.
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公开(公告)号：CA1233906A
公开(公告)日：1988-03-08
申请号：CA498310
申请日：1985-12-20
Applicant: IBM
Inventor： BLUM ARNOLD
Abstract: Test and Diagnostic Arrangement for Digital Computers The invention concerns arrangements and methods for error testing and diagnosing processors, which have logic subsystems interconnected by storage elements. In the error test and diagnostic mode the storage elements are connected in the form of shift register for the shift clock controlled application of test data to the processors and for receiving resultant data therefrom. The resultant data is compared to the desired resultant data and, in the case of a mismatch, an error indicator is set to initiate further action. When testing for the correct implementation of operations and operational secondary functions, a signature generator circuit is provided. The generator circuit includes a test accumulator for accumulating the test and resultant data from the storage elements and a test clock generator and counter for controlling the accumulation. A test memory provides test programs consisting of test data, desired result data and a list of the instructions from the processor instruction set which are to be tested. The signature generator circuit is connected to an interface register and/or a system bus of the processor. The stages of the interface register include the shift register formed by the storage elements.
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公开(公告)号：FR2406851B1
公开(公告)日：1986-04-11
申请号：FR7828926
申请日：1978-10-02
Applicant: IBM
Inventor： BAZLEN DIETER , BERGER ROLF , BLUM ARNOLD , BOCK DIETRICH W , CHILINSKI HERBERT , GENG HELLMUTH R , HAJDU JOHANN , IRRO FRITZ , NEUBER SIEGFRIED , WILLE UDO
IPC: G06F9/22
Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.
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Patent Agency Ranking
公开(公告)号：DE2965213D1
公开(公告)日：1983-05-19
申请号：DE2965213
申请日：1979-10-23
Applicant: IBM
Inventor： BLUM ARNOLD
Abstract: In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuitry is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed. The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.
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公开(公告)号：DE2963788D1
公开(公告)日：1982-11-11
申请号：DE2963788
申请日：1979-10-23
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHULZE-SCHOLLING HERMANN , SPATH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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公开(公告)号：AU5355379A
公开(公告)日：1980-06-19
申请号：AU5355379
申请日：1979-12-06
Applicant: IBM
Inventor： BLUM ARNOLD
Abstract: In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connected to all of the T-rings by lines of equal length forces the individual T-rings to operate synchronously and keeps them operating in such a manner. In addition, reset circuitry is provided for forcing all of the T-rings to their first timing interval for initial synchronization thereof or, at an appropriate time, when a micro instruction requiring less than the maximum number of available T-ring timing signals is executed. The timing signals which are locally produced are subject to little delay on their way to the various local switching points. Thus, the entire system can be operated at a higher oscillator or master clock frequency to take advantage of the enhanced processing and transfer speeds of modern, highly integrated circuit chips.
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公开(公告)号：CH601857A5
公开(公告)日：1978-07-14
申请号：CH1235876
申请日：1976-09-30
Applicant: IBM
Inventor： BLUM ARNOLD , HEYDEN HORST VON DER , IRRO FRITZ , RICHTER STEPHAN
IPC: G06F12/00 , G06F9/22 , G06F9/26 , G06F9/28 , G06F9/318 , G06F9/38 , G06F9/46 , G06F9/48 , G06F12/06 , G06F15/16 , G06F15/177 , G06F9/19
Abstract: 1533770 Data processing INTERNATIONAL BUSINESS MACHINES CORP 26 Oct 1976 [12 Dec 1975] 44531/76 Heading G4A In a multiprogrammed system in which time slices are allocated to programs by chained index words, the functions of specified types of instructions in specified programs are varied if certain external and/or internal non-program conditions are satisfied. The index words are held in a store 34, each word comprising a pointer which identifies which of a number of microprograms in a control store 20 is allocated the current time slice and a link address which points to a location in a store 36 holding the address of the next index word in store 34. The number of time slices allocated to any given micro-program by the index words in store 34 may be varied. The pointer from the current word accesses a micro-program pointer from a store 38 and the micro-program pointer in turn accesses the address of the next instruction for the relevant micro-program from a store 32. The current micro-program pointer from store 38 is compared with a set of micro-program identifiers and the OP code of the next microinstruction read from the control store 20 is compared with a set of micro-instruction identifiers. If equality is detected from both comparisons and if predetermined processor internal and/or peripheral external status signals are present a function change control signal on line 11 is produced and modification information pointed to by micro-program (or possibly microinstruction) pointer register 25 is read out from a buffer 29. The decoded modification information may be used, for example, to modify the result from the ALU 51 by +1. The processor also includes a data local store 46 for A and B operands and ALU results. The store 46 may also be used for loading micro-program and micro-instruction identifiers into the comparison registers and modification information into buffer 29 under micro-instruction control. The modification arrangements allow for (micro)programming flexibility without increasing the size of the (micro-)instruction set.
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公开(公告)号：AU528615B2
公开(公告)日：1983-05-05
申请号：AU5343379
申请日：1979-12-04
Applicant: IBM
Inventor： BLUM ARNOLD , GENG HELLMUTH ROLAND , SCHOELLING HERMANN SCHULZE , SPAETH BERND
Abstract: In a data processing or transmission system which includes at least two synchronized clocks, for example-T-rings A and B which generate timing pulses Tai and Tbi for microinstruction execution, synchronism is checked by logic circuitry which receives pulses from the clocks. At least one of the pulses is delayed by one or more pulse period durations ti. The logic circuit output signal is used as an input to an indicator latch which is periodically set by an independent check oscillator or clock. In a preferred embodiment, the delays are introduced by master-slave flip-flops, which receive predetermined combinations of the T-signals and set by the independent check clock. Several delay latches and associated AND gates may be used for different logical combinations of delayed and undelayed T-signals. This scheme can easily be expanded to accommodate more than two synchronously operating clocks. These circuits check not only the instantaneous synchronism of the clocks, but also the correct sequencing of clock pulses. The check is also feasible if the T-ring counters are operated with a variable number of clock pulses per microinstruction execution.
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