公开(公告)号：JP2005123597A

公开(公告)日：2005-05-12

申请号：JP2004271982

申请日：2004-09-17

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： AJMERA ATUL C ,  BRYANT ANDRES ,  GILBERT PERCY V ,  GRIBELYUK MICHAEL A ,  MACIEJEWSKI EDWARD P ,  MO RENEE T ,  NARASIMHA SHREESH

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a gate electrode that avoids dielectric layer undercut during a silicide precleaning step. SOLUTION: A patterned gate stack includes a gate dielectric below a conductor having vertical sidewalls, and a dielectric layer is formed over the patterned gate stack and substrate surfaces. Nitride spacers are formed overlying the dielectric layer at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample and subsequently removed by an etch process such that only a portion of the nitride film ("plug") remains. The plug seals and encapsulates the dielectric layer underlying the each spacer, thus preventing the dielectric material from being undercut during the subsequent silicide precleaning process. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在硅化物预清洗步骤期间形成避免电介质层底切的栅电极的方法。 解决方案：图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，并且在图案化的栅极堆叠和衬底表面上形成介电层。 在每个垂直侧壁处形成覆盖电介质层的氮化物间隔物。 使用蚀刻工艺去除衬底表面上的电介质层，使得每个间隔物下面的电介质层的一部分保留。 然后，在整个样品上沉积氮化物层，然后通过蚀刻工艺去除，使得只有一部分氮化膜（“插塞”）保留。 塞子密封并封装每个间隔物下面的电介质层，从而防止在随后的硅化物预清洗过程中电介质材料被切下。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000332101A

公开(公告)日：2000-11-30

申请号：JP2000131432

申请日：2000-04-28

Applicant: IBM

Inventor： JEFFREY SCOTT BROWN ,  BRYANT ANDRES ,  ROBERT J GAUTHIER JR ,  MANN RANDY W ,  VOLDMAN STEVEN H

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/8248 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator(SOI) element having both an element which is completely depleted and an element which is partially depleted on a common substrate. SOLUTION: The semiconductor structure which has a continuous buried oxide layer 24 and multiple trench separate structures 33 and 35 and its formation are disclosed. The buried oxide layer is arranged in the substrate at >=2 trench separate structures in depth. The trench separate structures are variable in depth and it is not important whether the trench separate structures are in contact with the buried oxide layer or not. The two trench separate structures enter the substrate to the same or different depths. The trench separate structures provide insulating separation between areas in the substrate and the separated areas may include a semiconductor element. The semiconductor structure makes it easy to provide a digital element and an analog element on a common wafer. The dual-depth buried oxide layer facilitates the formation of an asymmetrical semiconductor structure.

公开(公告)号：JP2007142417A

公开(公告)日：2007-06-07

申请号：JP2006308667

申请日：2006-11-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  BRENT A ANDERSON ,  JEFFREY B JOHNSON

IPC: H01L21/336 ,  H01L21/283 ,  H01L29/41 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a trigate field effect transistor provided with a fin-shaped semiconductor body with a channel region and source/drain regions on either side of the channel region. SOLUTION: Thick gate dielectric layers separate the top surface and opposing sidewalls of the channel region from the gate conductor to suppress conductivity in the channel planes. A thin gate dielectric layer separates the upper corners of the channel region from the gate dielectric to optimize conductivity in the channel corners. To further emphasize the electric current in the channel corners, the source/drain regions can be formed only in the upper corners of the semiconductor body. Alternatively, source/drain extension regions can be formed only in the upper corners of the semiconductor body adjacent to the gate conductor and deep source/drain diffusion regions can be formed in the ends of the semiconductor body. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有鳍状半导体本体的三端场效应晶体管，沟道区域和沟道区两侧的源极/漏极区域。 解决方案：厚栅极电介质层将沟道区域的顶表面和相对侧壁与栅极导体分离，以抑制沟道平面中的导电性。 薄栅极电介质层将沟道区的上角与栅极电介质分离，以优化沟道角中的导电性。 为了进一步强调通道角中的电流，源极/漏极区域只能形成在半导体本体的上角处。 或者，源极/漏极延伸区域仅可以形成在与栅极导体相邻的半导体本体的上角处，并且可以在半导体本体的端部形成深的源极/漏极扩散区域。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000101093A

公开(公告)日：2000-04-07

申请号：JP24211799

申请日：1999-08-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  EDWARD J NOWACK ,  WILBUR D PRISER ,  MIN H TONG

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a device structure of SOI(silicon on isulator) CMOS (complementary metal oxide semiconductor) in which avalanche multiplication of current flowing through a device is increased when an FET(field effect transistor) is turned on and body charges are removed when the FET is turned off. SOLUTION: An FET having an electric floating body is substantially isolated electrically from a substrate. A high resistance path 16 for coupling the floating body is provided at the source. The resistor is operated as a floating body for active switching and a body grounded in waiting mode in order to reduce leakage current. The high resistance path has a resistance of at least 1 MΩ and made of polysilicon. The resistor is formed using a split polysilicon process for opening a hole in a first polysilicon layer in order that an embedded contact mask 19 brings a second polysilicon layer into contact with the substrate.

公开(公告)号：WO2009012276A3

公开(公告)日：2009-03-26

申请号：PCT/US2008070102

申请日：2008-07-16

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  NOWAK EDWARD J

IPC: H01L21/335

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7834 ,  H01L29/7835

Abstract: Disclosed are embodiments of an asymmetric field effect transistor structure (200a-c) and a method of forming the structure in which both series resistance in the source region (204, 304) (Rs) and gate (210, 310) to drain ((205, 305) capacitance (Cgd) are reduced in order to provide optimal performance (i.e., to provide improved drive current with minimal circuit delay) Specifically, different heights (214, 215) of the source (204) and drain regions (205) and/or different distances (351, 352) between the source (304) and drain regions (305) and the gate (210, 310) are tailored to minimize series resistance in the source region (204, 305) (i.e., in order to ensure that series resistance is less than a predetermined resistance value) and in order to simultaneously to minimize gate (210, 310) to drain (205, 305) capacitance (i.e., in order to simultaneously ensure that gate ( 210, 310) to drain (205, 305) capacitance is less than a predetermined capacitance value).

Abstract translation: 公开了不对称场效应晶体管结构（200a-c）的实施例以及形成其中源极区（204,304）（Rs）和栅极（210,310）中的两个串联电阻漏极（（ （204）和漏极区域（205）的不同高度（214,215），以便提供最佳性能（即，提供具有最小电路延迟的改进的驱动电流） 和/或源极（304）和漏极区域（305）与栅极（210,310）之间的不同距离（351,352）被调整为使源极区域（204,305）中的串联电阻最小化（即，按顺序 以确保串联电阻小于预定电阻值）并且为了同时使栅极（210,310）与漏极（205,305）的电容最小化（即，为了同时确保栅极（210,310）至 漏极（205,305）电容小于预定电容值）。

公开(公告)号：WO2009012295A3

公开(公告)日：2009-03-12

申请号：PCT/US2008070143

申请日：2008-07-16

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  ELLIS-MONAGHAN JOHN J ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  ELLIS-MONAGHAN JOHN J ,  NOWAK EDWARD J

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

Abstract: Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (350) (i.e., a multiple fin dual-gate or tri-gate field effect transistor) (300, 300a, 300b) in which the multiple fins arc partially or completely merged by a highly conductive material (360a, 360b) (e.g., a metal suicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions (375a-b). Merging the semiconductor fins (350) in this manner also allows each of the source/drain regions (375a-b) to be contacted by a single contact via as well as more flexible placement of that contact via.

Abstract translation: 本文公开了多个鳍片式场效应晶体管（350）（即，多鳍式双栅极或三栅极场效应晶体管）（300,300a，300b）的实施例，其中多个鳍片部分地或完全地 由高导电材料（360a，360b）（例如金属硅化物）合并。 以这种方式合并鳍片允许串联电阻最小化，而栅极和源极/漏极区域（375a-b）之间的寄生电容几乎没有增加（如果有的话）。 以这种方式合并半导体鳍（350）还允许每个源极/漏极区（375a-b）通过单个接触通孔接触，以及该接触通孔更灵活的放置。

公开(公告)号：WO2008064227A3

公开(公告)日：2008-09-18

申请号：PCT/US2007085246

申请日：2007-11-20

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L21/8238

CPC classification number: H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

Abstract: A semiconductor device (80,85) including semiconductor material (35,40) having a bend and a trench feature formed at the bend, and a gate structure (45,50) at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

Abstract translation: 一种包括半导体材料（35,40）的半导体器件（80,85），所述半导体材料具有在所述弯曲处形成的弯曲部和沟槽特征以及至少部分地设置在所述沟槽特征中的栅极结构（45,50）。 一种制造半导体结构的方法，包括：在层上形成具有沟槽特征的半导体材料;至少部分地在沟槽特征中形成栅极结构;以及弯曲半导体材料，使得在半导体材料中的反转沟道 栅极结构的区域。

公开(公告)号：WO2010138278A3

公开(公告)日：2011-02-03

申请号：PCT/US2010033469

申请日：2010-05-04

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L21/8244 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L21/823481 ,  H01L21/823493 ,  H01L27/092 ,  H01L27/11 ,  H01L27/1104

Abstract: Disclosed are embodiments of an improved integrated circuit device structure (200) (e.g., a static random access memory array structure or other integrated circuit device structure incorporating both P-type and N-type devices) (121a and 121b) and a method of forming the structure that uses DTI regions (160) for all inter- well and intra- well isolation and, thereby provides a low-cost isolation scheme that avoids FET width variations due to STI-DTI misalignment. Furthermore, because the DTI regions (160) used for intra- well isolation effectively create some floating well sections, (203) which must each be connected to a supply voltage (e.g., Vdd) (280) to prevent threshold voltage (Vt) variations, the disclosed integrated circuit device also includes a shared contact (280) to a junction between the diffusion regions (221 and 222) of adjacent devices (121a and 121b) and an underlying floating well section (205). This shared contact (280) eliminates the cost and area penalties that would be incurred if a discrete supply voltage contact was required for each floating well section (205).

Abstract translation: 公开了改进的集成电路器件结构（200）（例如，并入P型和N型器件的静态随机存取存储器阵列结构或其他集成电路器件结构）（121a和121b）的实施例和形成方法 使用DTI区域（160）进行所有井间和井内隔离的结构，从而提供了一种低成本隔离方案，可避免由于STI-DTI失准导致的FET宽度变化。 此外，由于用于井内隔离的DTI区域（160）有效地产生一些浮动井区段（203），其必须各自连接到电源电压（例如Vdd）（280），以防止阈值电压（Vt）变化 所公开的集成电路器件还包括到相邻器件（121a和121b）的扩散区域（221和222）与下面的浮动阱区段（205）之间的连接处的共用触点（280）。 这种共享联系人（280）消除了如果每个浮动井段（205）需要离散的电源电压接触，将会产生的成本和面积的惩罚。

公开(公告)号：WO2010008748A8

公开(公告)日：2010-04-22

申请号：PCT/US2009047719

申请日：2009-06-18

Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/334

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design structure (100, FIG. 1a) is provided for spacer fill structures (100 and 300) and, more particularly, spacer fill structures (100 and 300), a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes (100) in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

Abstract translation: 提供了用于间隔物填充结构（100和300）的设计结构（100，图1a），更具体地，提供了间隔件填充结构（100和300），制造方法和用于减小装置变化的设计结构。 该结构包括在器件的不同区域中的多个虚拟填充形状（100），其被配置为使得栅极周边与栅极面积比将导致整个芯片的总周边密度是均匀的。

公开(公告)号：WO2007011496A3

公开(公告)日：2008-05-29

申请号：PCT/US2006024701

申请日：2006-06-26

Applicant: IBM ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  WILLIAMS RICHARD Q

IPC: H01L21/84 ,  H01L27/108

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/0811 ,  H01L28/40 ,  H01L29/78648 ,  Y10T436/235 ,  Y10T436/25125 ,  Y10T436/2525 ,  Y10T436/25375

Abstract: A method of manufacture and device for a dual-gate CMOS structure. The structure includes a first plate (106a-d) in an insulating layer (100) and a second plate (110a-d) above the insulating layer electrically corresponding to the first plate. An isolation structure (108a-d) is between the first plate and the second plate.

Abstract translation: 一种双栅极CMOS结构的制造方法和器件。 该结构包括绝缘层（100）中的第一板（106a-d）和与第一板电对应的绝缘层上方的第二板（110a-d）。 隔离结构（108a-d）位于第一板和第二板之间。