公开(公告)号：DE602008004169D1

公开(公告)日：2011-02-03

申请号：DE602008004169

申请日：2008-07-21

Applicant: IBM

Inventor： CASES MOISES ,  PHAM NAM HUU ,  ARAUJO DANIEL N DE ,  MUTNURY BHYRAV MURTHY ,  DREPS DANIEL MARK

IPC: G11C29/56 ,  G06F11/273

公开(公告)号：DE3373964D1

公开(公告)日：1987-11-05

申请号：DE3373964

申请日：1983-06-16

Applicant: IBM

Inventor： CASES MOISES ,  KRAFT WAYNE RICHARD ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY

IPC: H03K19/096 ,  H03K19/177 ,  H03K19/094 ,  H03K5/15

Abstract: Circuit for speeding up transfers of charges in a Programmed Logic Array structure, formed by FET devices (3) in serially chained charge transfer circuits, comprising a level shifting circuit (21) integrated into bit partitioning stages of the structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings at the inputs of the AND array chains (24) as well as decreasing operational delays of the latter stage, discrete capacitance, (29), added at the output end of the OR array stage (10) for sustaining and reinforcing charge conditions accumulated in that stage prior to readout of that stage, and a source of time related clocking functions (Cp1-Cv3) coupled to stages of the modified structures, with timing relationship selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

公开(公告)号：DE3364802D1

公开(公告)日：1986-09-04

申请号：DE3364802

申请日：1983-02-01

Applicant: IBM

Inventor： KRAFT WAYNE RICHARD ,  CASES MOISES ,  STAHL WILLIAM LEONARD ,  THOMA NANDOR GYORGY ,  WYATT VIRGIL DEAN

IPC: H01L21/822 ,  G06F9/22 ,  G06F9/26 ,  G06F9/28 ,  H01L21/82 ,  H01L27/04 ,  H03K19/173 ,  H03K19/177

公开(公告)号：DE2854009A1

公开(公告)日：1979-07-12

申请号：DE2854009

申请日：1978-12-14

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  CASES MOISES ,  CHANG FUNG YUEL

IPC: G11C11/56 ,  G11C19/28 ,  G11C27/04 ,  H01L27/10 ,  H01L27/105 ,  H03H11/26 ,  G11C7/00 ,  G11C11/24

公开(公告)号：FR2400804A1

公开(公告)日：1979-03-16

申请号：FR7821332

申请日：1978-07-12

Applicant: IBM

Inventor： CASES MOISES ,  CHANG FUNG Y ,  RUBIN BARRY J

IPC: G06G7/16 ,  G11C27/04 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H03H15/02 ,  H03K

Abstract: A charge coupled device analog multiplier is used to weigh the sampled and delayed signals for a transversal filter. The digital filter coefficients for the analog multiplier can be electrically programmed and therefore dynamic time-varying systems, such as matched filters, can be designed with reduced circuit complexity. The digital filter includes means for sampling without destroying an analog signal at various points and providing voltages proportional to each sampled signal. The voltages are separately applied to a charge coupled device analog multiplier which accepts the voltages and provides means for multiplying the digital filter coefficient by the analog voltage. The multiplied sample signal is then dumped into a means for summing all of the weighted sample signals to produce an analog signal modified by the digital filter coefficients.

公开(公告)号：DE2835497A1

公开(公告)日：1979-03-01

申请号：DE2835497

申请日：1978-08-12

Applicant: IBM

Inventor： CASES MOISES ,  CHANG FUNG YUEL ,  RUBIN BARRY JAY

IPC: G06G7/16 ,  G11C27/04 ,  H01L21/339 ,  H01L29/76 ,  H01L29/762 ,  H03H15/02 ,  H03H11/00

Abstract: A charge coupled device analog multiplier is used to weigh the sampled and delayed signals for a transversal filter. The digital filter coefficients for the analog multiplier can be electrically programmed and therefore dynamic time-varying systems, such as matched filters, can be designed with reduced circuit complexity. The digital filter includes means for sampling without destroying an analog signal at various points and providing voltages proportional to each sampled signal. The voltages are separately applied to a charge coupled device analog multiplier which accepts the voltages and provides means for multiplying the digital filter coefficient by the analog voltage. The multiplied sample signal is then dumped into a means for summing all of the weighted sample signals to produce an analog signal modified by the digital filter coefficients.