公开(公告)号：EP1402386A4

公开(公告)日：2009-06-24

申请号：EP02721138

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  H04L29/12 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：EP1381963A4

公开(公告)日：2008-02-13

申请号：EP02707876

申请日：2002-02-25

Applicant: IBM

Inventor： BHANOT GYAN V ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  STEINMACHER-BUROW BURKHARD D ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：EP1379933A4

公开(公告)日：2007-10-17

申请号：EP02714980

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  HOENICKE DIRK ,  OHMACHT MARTIN ,  STEINMARCHER-BUROW BURKHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F1/00

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：EP1381958A4

公开(公告)日：2007-05-09

申请号：EP02717497

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPARA MARK E ,  HEIDELBERGER PHILIP ,  KOPSCAY GERARD V ,  STEINMACHER-BUROW BURKHARD D ,  TAKKEN TODD E

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/00 ,  G06F15/76

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

Abstract translation: 一种用于在计算结构中生成全局异步信号的系统和方法。 特别地，实现全局中断和屏障网络，其实现用于根据处理算法来生成全局中断和屏障信号的逻辑，所述全局中断和屏障信号用于控制由计算结构的选定处理节点（12）处的处理元件执行的全局异步操作; 并且包括用于经由低等待时间路径将全局中断和屏障信号传送到元件的处理节点（12）的物理互连。 全局异步信号分别在处理节点（12）处选择用于最佳化处理算法的性能的时间启动中断和屏障操作。 在一个实施例中，全局中断和屏障网络在包括由多个独立网络互连的多个处理节点的可扩展的大规模并行超级计算设备结构中实现。

公开(公告)号：EP1378090A4

公开(公告)日：2005-02-09

申请号：EP02723233

申请日：2002-02-25

Applicant: IBM

Inventor： BARRETT WAYNE M ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  JACKSON RORY D ,  KOPCSAY GERARD V ,  NATHANSON BEN J ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  H04L7/00 ,  H03D3/24 ,  H04B10/08

CPC classification number: H05K7/20836 ,  F24F11/77 ,  G06F9/52 ,  G06F9/526 ,  G06F15/17381 ,  G06F17/142 ,  G09G5/008 ,  H04L7/0338 ,  Y02B30/746

Abstract: A fan module including: two or more individual fans, each fan having an air movement means and a motor engaged with the air movement means for accelerating air entering each of the two or more individual fans; a temperature sensor for sensing a temperature associated with the two or more fans and for outputting a first signal corresponding to the temperature; rotational speed sensor for outputting a second signal corresponding to a rotational speed of each of the two or more fans; and a processor for receiving the first and second signals and controlling the two or more individual fans based on the first and second signals.

公开(公告)号：CA2436413C

公开(公告)日：2011-09-27

申请号：CA2436413

申请日：2002-02-25

Applicant: IBM

Inventor： BHANOT GYAN V ,  BLUMRICH MATTHIAS A ,  CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  STEINMACHER-BUROW BURKHARD D ,  TAKKEN TODD E ,  VRANAS PAVLOS M

IPC: G06F11/10 ,  H04L1/18 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04J3/02 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Class network routing is implemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With class network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast, Class network routing is also applied to dense matrix inversion algorithms on distributed memory parallel supercomputers with hardware class function (multicast) capability. This is achieved by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware class functions, which results in faster execution times.

公开(公告)号：CA2437629A1

公开(公告)日：2002-09-06

申请号：CA2437629

申请日：2002-02-25

Applicant: IBM

Inventor： VRANAS PAVLOS M ,  CHEN DONG ,  BLUMRICH MATTHIAS A ,  BHANOT GYAN V ,  STEINMACHER-BUROW BURKHARD D ,  HEIDELBERGER PHILIP ,  GIAMPAPA MARK E ,  GARA ALAN G

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Methods and systems for performing arithmetic functions. In accordance with a first aspect of the invention, methods and apparatus are provided, working i n conjunction of software algorithms and hardware implementation of class network routing, to achieve a very significant reduction in the time require d for global arithmetic operation on the torus. Therefore, it leads to greater scalability of applications running on large parallel machines. The inventio n involves three steps in improving the efficiency and accuracy of global operations: (1) Ensuring, when necessary, that all the nodes do the global operation on the data in the same order and so obtain a unique answer, independent of roundoff error; (2) Using the topology of the torus to minimi ze the number of hops and the bidirectional capabilities of the network to redu ce the number of time steps in the data transfer operation to an absolute minimum; and (3) Using class function routing to reduce latency in the data transfer. With the method of this invention, every single element is injecte d into the network only once and it will be stored and forwarded without any further software overhead. In accordance with a second aspect of the invention, methods and systems are provided to efficiently implement global arithmetic operations on a network that supports the global combining operations. The latency of doing such global operations are greatly reduced by using these methods (Figure 4, node0, node1, node2, node3).

公开(公告)号：ES2346409T3

公开(公告)日：2010-10-15

申请号：ES02721138

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  TAKKEN TODD E

IPC: G06F11/10 ,  H04L29/12 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: Procedimiento para asignar, de manera única, una dirección MAC (400) a un dispositivo de computación en un nodo (205) de un sistema de computación masivamente paralelo que comprende una pluralidad de dichos nodos, caracterizado porque el procedimiento comprende: programar el dispositivo de computación para codificar una ubicación física del dispositivo de computación en la dirección MAC; usar un número predeterminado de bits (410) de la dirección MAC para la etapa de codificación, en la que la ubicación física del dispositivo de computación es descrita de manera única.

公开(公告)号：DE60237433D1

公开(公告)日：2010-10-07

申请号：DE60237433

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  CHIU GEORGE L ,  CIPOLLA THOMAS M ,  COTEUS PAUL W ,  GARA ALAN G ,  GIAMPAPA MARK E ,  HEIDELBERGER PHILIP ,  KOPSCAY GERALD V ,  MOK LAWRENCE S ,  TAKKEN TODD E

IPC: G06F11/10 ,  G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

公开(公告)号：AT479147T

公开(公告)日：2010-09-15

申请号：AT02733807

申请日：2002-02-25

Applicant: IBM

Inventor： BLUMRICH MATTHIAS A ,  CHEN DONG ,  CHIU GEORGE L ,  CIPOLLA THOMAS ,  COTEUS PAUL ,  GARA ALAN ,  GIAMPAPA MARK ,  HEIDELBERGER PHILIP ,  KOPSCAY GERALD ,  MOK LAWRENCE ,  TAKKEN TODD

IPC: G06F11/10 ,  G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/00 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20

Abstract: A novel massively parallel supercomputer of hundreds of teraOPS-scale includes node architectures based upon System-On-a-Chip technology, i.e., each processing node comprises a single Application Specific Integrated Circuit (ASIC). Within each ASIC node is a plurality of processing elements each of which consists of a central processing unit (CPU) and plurality of floating point processors to enable optimal balance of computational performance, packaging density, low cost, and power and cooling requirements. The plurality of processors within a single node individually or simultaneously work on any combination of computation or communication as required by the particular algorithm being solved. The system-on-a-chip ASIC nodes are interconnected by multiple independent networks that optimally maximizes packet communications throughput and minimizes latency. The multiple networks include three high-speed networks for parallel algorithm message passing including a Torus, Global Tree, and a Global Asynchronous network that provides global barrier and notification functions.