公开(公告)号：CA2026737A1

公开(公告)日：1991-05-14

申请号：CA2026737

申请日：1990-10-02

Applicant: IBM

Inventor： GARCIA SERAFIN J E JR ,  CHISHOLM DOUGLAS R ,  KALMAN DEAN A ,  PADGETT RUSSELL S ,  YODER ROBERT D

IPC: G06F13/32 ,  G06F13/362

Abstract: A plurality of specialized controllers, e.g. 202, 204 & 206, each one adapted to control a particular type of data transfer operation, control the flow of data between a system bus 104 and a local bus 106 on a computer adapter card 102. When the Direct Memory Access DMA controller 202 is controlling a DMA operation on the local bus, certain other controllers 204 & 206 can break-in to the current DMA operation, temporarily halting the DMA operation until the other controller has completed its data transfer operation. To break-in to a DMA operation, handshaking signals between the DMA controller and the local bus interface circuit 212 are temporarily blocked by blocking signals from a break-in logic circuit 210 . The break-in circuit includes a four-state state machine to block the handshaking signals at the appropriate times, and to signal the interrupting controller to begin its data transfer operation. When breaking-in to a DMA operation in this manner, the operation of the DMA controller is not altered; instead, to the DMA controller, it appears that the local bus interface circuit is merely slow to respond with its acknowledge handshake.

公开(公告)号：BR8704624A

公开(公告)日：1988-04-26

申请号：BR8704624

申请日：1987-09-04

Applicant: IBM

Inventor： BOURKE DONALD G ,  CHISHOLM DOUGLAS R ,  FLOAT GREGORY D ,  KELLEY RICHARD A ,  LIU ROY Y ,  MALMQUIST CARL A ,  NELSON JOHN M ,  PERKINS CHARLES B JR ,  PLACE RICHARD L ,  SCHWERMER HARTMUT R ,  WILSON JOHN DAVID

IPC: G06F13/36 ,  G06F13/40 ,  G06F13/20

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation.

公开(公告)号：PH31356A

公开(公告)日：1998-07-31

申请号：PH40473

申请日：1990-05-03

Applicant: IBM

Inventor： BONEVENTO FRANCIS M ,  CHISHOLM DOUGLAS R ,  DOODS SAMMY D ,  DESAI DHRUVKUMAR M ,  MANDESE ERNEST N ,  MCNEILL ANDREW B ,  MENDELSON RICHARD N

IPC: G06F13/12 ,  G06F13/24

Abstract: A Command interface includes ports for transferring information between a host processor and at least one intelligent subsystem which may have attached devices. A Command Interface port receives either a direct command or an indirect command from the host processor, which commands are indicative of a type of operation to be performed by the one subsystem or an attached device. An Attention port receives a code from the host processor which is indicative of which one of the direct command or the indirect command is received at the Command Interface port, and which is also indicative of which of the one intelligent subsystem or a device is to execute the command. A command busy/status port receives a code from the one intelligent subsystem which is indicative of whether or not the Command Interface port and the Attention port are busy, and whether or not the one intelligent subsystem is accepting or rejecting commands. The host processor can read this port without altering or updating the code.

公开(公告)号：CA1297994C

公开(公告)日：1992-03-24

申请号：CA544335

申请日：1987-08-12

Applicant: IBM

Inventor： BOURKE DONALL G ,  CHISHOLM DOUGLAS R ,  FLOAT GREGORY D ,  KELLEY RICHARD A ,  LIU ROY Y ,  MALMQUIST CARL A ,  NELSON JOHN M ,  PERKINS CHARLES B ,  PLACE RICHARD L ,  SCHWERMER HARTMUT R ,  WILSON JOHN D

IPC: G06F13/36 ,  G06F13/40

Abstract: In a data processing system, an input output bus unit (IOBU) is connected to one end of an input output interface controller (IOIC) via an asynchronous bus. The other end of the IOIC is connected to a storage controller (SC) and an input output interface unit (IOIU) via a synchronous bus. The SC and IOIU are connected to a memory unit and an instruction processing unit. The asynchronous bus, which is comprised of three sub-buses and a control bus, conducts signals between the IOIC and an IOBU in an asynchronous "handshaking" manner. The synchronous bus, which is comprised of two sub-buses and a control bus, conducts signals between the IOIC and the SC/IOIU in an synchronous manner. The IOIC, interconnected between the synchronous bus and asynchronous bus, functions as a buffer between the faster synchronous bus and the slower asynchronous bus. Various operations are performed between an IOBU and the memory unit via the asynchronous bus, IOIC, synchronous bus, and SC/IOIU, such as a unit operation, a storage operation, and a message acceptance operation. EN980633

公开(公告)号：BR9005633A

公开(公告)日：1991-09-17

申请号：BR9005633

申请日：1990-11-07

Applicant: IBM

Inventor： PADGETT RUSSEL S ,  CHISHOLM DOUGLAS R ,  GARCIA SERAFIN JOSE E JR ,  ALVAREZ RAFAEL ,  KALMAN DEAL A ,  YODER ROBERT D

IPC: G06F12/06 ,  G06F12/02 ,  G06F13/16 ,  G06F13/14

Abstract: A selected address within one of two segments of a memory space (124) of a second address/data bus (116), can be accessed from a first bus (102) through one of two data registers (136 and 138). In addition, the location of the two segments within the memory space of the second bus is selectable through two segment registers (148 and 150), which are accessed from the first bus through the first data register (136). A two byte wide "mode" register (126 and 128), which can be directly accessed from the first bus, stores data within three ranges. When the mode register data is within the first range, a selected segment register can be accessed through the first data register. A first value within this range selects the first segment register (148), while a second value selects the second segment register (150). Data loaded into the first and second segment registers points to first and second segments of the second memory space, respectively. When the mode register data is within the second range, this data functions as a pointer to select an address within a selected segment. The selected address is accessed through the data registers; the first data register (136) accessing the selected address in the first segment, while the second data register (138) accesses the selected address in the second segment. After a selected address has been accessed, an auto-increment circuit increments the mode register so that the next sequential address in the selected segment can be accessed without having to reload the mode register. When the mode register data is within the third range, the two data registers can be directly accessed from the first bus.

公开(公告)号：CA1158778A

公开(公告)日：1983-12-13

申请号：CA378809

申请日：1981-06-02

Applicant: IBM

Inventor： CHISHOLM DOUGLAS R ,  KURTZ HOBART L JR

IPC: G06F13/14 ,  G06F12/02 ,  G06F12/06 ,  G06F3/00 ,  G06F15/00

Abstract: BC9-80-012 DYNAMIC DEVICE ADDRESS ASSIGNMENT MECHANISM FOR A DATA PROCESSING SYSTEM A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.

公开(公告)号：BR8104224A

公开(公告)日：1982-03-23

申请号：BR8104224

申请日：1981-07-02

Applicant: IBM

Inventor： CHISHOLM DOUGLAS R ,  KURTZ HOBART L

IPC: G06F13/14 ,  G06F12/02 ,  G06F12/06 ,  G06F3/04

Abstract: A peripheral device address assignment mechanism is described which does not require the use of plugboards or jumpers. This mechanism enables a host processor to select any desired peripheral device and set its device address to any desired value at any desired time. This is accomplished by providing each peripheral device control unit with a loadable device address register for holding the device address assigned to its peripheral device. Each device control unit is further provided with circuitry responsive to the appearance of a unique I/O command on the processor I/O bus and to the activation of a unique set of the I/O bus data lines by the processor for loading into its device address register the desired device address value as supplied thereto by the processor via the I/O bus.