公开(公告)号：WO2007084907A3

公开(公告)日：2007-12-21

申请号：PCT/US2007060615

申请日：2007-01-17

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  LANDERS WILLIAM F ,  ZUPANSKI-NIELSEN DONNA S

Inventor： DAUBENSPECK TIMOTHY H ,  LANDERS WILLIAM F ,  ZUPANSKI-NIELSEN DONNA S

IPC: H01L21/44

CPC classification number: H01L21/288 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05575 ,  H01L2224/05599 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/01015

Abstract: The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure (30) containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect (22) by a selective electroless plating process.

Abstract translation: 本发明涉及一种用于制造具有基本上不含铝的最后一级铜对C4连接的半导体器件的方法。 具体地说，最后一级的铜对C4连接包括含有CoWP，NiMoP，NiMoB，NiReP，NiWP及其组合的界面帽结构（30）。 优选地，界面帽结构包括至少一个CoWP层。 这种CoWP层可以通过选择性无电镀方法容易地在最后一级的铜互连（22）上形成。

公开(公告)号：WO2005013330A2

公开(公告)日：2005-02-10

申请号：PCT/US2004024228

申请日：2004-07-28

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

IPC: H01L20060101 ,  H01L21/301 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/78 ,  H01L23/00 ,  H01L23/28 ,  H01L23/58 ,  H01L

CPC classification number: H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A crack stop (28) for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal (12) is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

Abstract translation: 使用金属互连在集成电路（IC）上形成集成电路（IC）的低K电介质材料的裂缝阻挡（28），所述金属互连在低K电介质中不形成自钝化氧化物层（例如铜或银互连） 材料以防止在切割操作期间由于沿着IC芯片的外围边缘形成的碎裂和破裂而导致对IC芯片的有源区域的损坏。 防潮层或边缘密封件（12）形成为沿着IC芯片的有效区域的外周边缘定位的金属堆叠。 通过位于IC芯片的外周上的防潮/边缘密封件外侧的至少一个沟槽或槽来形成止裂件。

公开(公告)号：DE112012004768T5

公开(公告)日：2014-11-06

申请号：DE112012004768

申请日：2012-08-29

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  QUESTAD DAVID L ,  SAUTER WOLFGANG ,  SULLIVAN TIMOTHY D

IPC: H01L23/48

Abstract: Ein topographisches Merkmal (305) ist in unmittelbarer Nähe zu einer leitfähigen Bond-Kontaktstelle (235) ausgebildet, die dazu verwendet wird, einen Lötkontakthügel (160) mit einem Halbleiter-Chip (140) zu verbinden. Das topographische Merkmal (305) ist durch einen Zwischenraum (310) von der leitfähigen Bond-Kontaktstelle (235) getrennt. Bei einer Ausführungsform ist das topographische Merkmal (305) an einer Stelle ausgebildet, die sich etwas jenseits der äußeren Begrenzung des Lötkontakthügels (160) befindet, wobei eine Kante des Kontakthügels (160) vertikal so ausgerichtet ist, dass sie mit dem Zwischenraum (310) zusammenfällt, der die leitfähige Bond-Kontaktstelle (235) von dem topographischen Merkmal (305) trennt. Das topographische Merkmal (305) stellt eine Erhöhung der Dicke einer nichtleitfähigen Schicht (240), die über dem Halbleiter-Chip (140) und der leitfähigen Bond-Kontaktstelle (235) angeordnet ist, und eine Verspannungspufferung bereit.

公开(公告)号：DE3852619D1

公开(公告)日：1995-02-09

申请号：DE3852619

申请日：1988-10-31

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  ICHISHITA FAITH S

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/31

Abstract: A plasma comprised of a fluorinated gas, an oxidant, and up to 15%-20% chlorofluorocarbon gas etches non-insulating materials such as tungsten and silicon at very high etch rates while providing enhanced etch rate ratios to photoresist and insulators.

公开(公告)号：DE69220393T2

公开(公告)日：1998-01-15

申请号：DE69220393

申请日：1992-02-04

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  DAUBENSPECK TIMOTHY H ,  LUCE STEPHEN E ,  POLEY DENIS J ,  PREVITI-KELLEY ROSEMARY A ,  VIENS GARY P ,  YOON JUNG H

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：DE69220393D1

公开(公告)日：1997-07-24

申请号：DE69220393

申请日：1992-02-04

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  DAUBENSPECK TIMOTHY H ,  LUCE STEPHEN E ,  POLEY DENIS J ,  PREVITI-KELLEY ROSEMARY A ,  VIENS GARY P ,  YOON JUNG H

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：DE3852619T2

公开(公告)日：1995-07-06

申请号：DE3852619

申请日：1988-10-31

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  ICHISHITA FAITH S

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/306 ,  H01L21/31

Abstract: A plasma comprised of a fluorinated gas, an oxidant, and up to 15%-20% chlorofluorocarbon gas etches non-insulating materials such as tungsten and silicon at very high etch rates while providing enhanced etch rate ratios to photoresist and insulators.

公开(公告)号：ES2221602T3

公开(公告)日：2005-01-01

申请号：ES00107337

申请日：2000-04-04

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  MOTSIFF WILLIAM T

IPC: H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525

Abstract: Un chip semiconductor que tiene una disposición fusible que comprende un conductor eléctrico que tiene una primera capa de un primer material (24) eléctricamente conductor y una segunda capa de un segundo material (26) eléctricamente conductor, teniendo dicha segunda capa un espesor, una composición y unas propiedades ópticas tales que la combinación de dicha segunda capa con dicha primera capa proporciona características de gran absorción de la energía de la radiación infrarroja incidente emitida desde un láser, minimizando así la cantidad de dicha energía requerida para suprimir, o fundir, la disposición fusible, caracterizado porque, dicha primera capa de dicho primer material (24) está provista de una parte selectiva rebajada (32) y dicha parte selectiva rebajada (32) está llena con dicha segunda capa de dicho segundo material (26).

公开(公告)号：AT270463T

公开(公告)日：2004-07-15

申请号：AT00107337

申请日：2000-04-04

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  MOTSIFF WILLIAM T

IPC: H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525

Abstract: A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy. Fabrication methods for providing overlaying material to the entire fuse link line, or to selective portions of the fuse link line are presented.