公开(公告)号：EP1687850A4

公开(公告)日：2008-06-25

申请号：EP04779326

申请日：2004-07-28

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

IPC: H01L23/28 ,  H01L20060101 ,  H01L21/301 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/78 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A crack stop (28) for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal (12) is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

公开(公告)号：EP2020023A4

公开(公告)日：2012-09-19

申请号：EP07761307

申请日：2007-04-26

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

公开(公告)号：JPH113965A

公开(公告)日：1999-01-06

申请号：JP10935898

申请日：1998-04-20

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  FERENCE THOMAS G ,  HOLMES STEVEN J

IPC: H01L23/52 ,  H01L23/48 ,  H01L25/065

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which a wire lead is not covered and a chip access face is insulated. SOLUTION: The semiconductor device has a conductive lead 25 which is positioned inside of a first insulating material 22 and a tip end of which is exposed. In this case, the first insulating material 22 is alternately provided between first and second insulated integrated circuit chips 10 and 16. The first insulating material 22 is etched to form a recess therein and thereafter, a second insulating material 34 is provided on an access face 30 of the first and second chips 10 and 16 and on an inside face of the recess. Next a tip end 25 of the wire lead is exposed by chemical-mechanical polishing or by a wet-etching/ developing process.

公开(公告)号：JP2000323580A

公开(公告)日：2000-11-24

申请号：JP2000124143

申请日：2000-04-25

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  MOTSIFF WILLIAM T

IPC: H01L21/3205 ,  H01L21/82 ,  H01L23/52 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide a copper fuse of high laser absorption which minimizes laser energy required for erasing the fuse section of a conductor. SOLUTION: Metal wiring include a fuse segment, consisting of at least two kinds of metallic stacks. A material 24 of the metallic stack is a main conductor consisting of copper, and also the metal (that is, the conductor whose composition is mainly tungsten or titanium-tungsten) 26 of the upper layer has a prescribed thickness and optical properties which are selected so that the coupling between the lower metal 24 and the upper metal 26 gives high absorptive property to incident energy.

公开(公告)号：WO2007127816A2

公开(公告)日：2007-11-08

申请号：PCT/US2007067449

申请日：2007-04-26

Applicant: IBM ,  FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

Inventor： FAROOQ MUKTA G ,  DAUBENSPECK TIMOTHY H ,  SAUTER WOLFGANG ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  PETRARCA KEVIN S

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads 37 with ball limiting metallization on an integrated circuit chip 30 by using a damascene process and preferably Cu metallization 32 in the chip 30 and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad 52 is formed in the top insulating layer 51 and it also serves as the final level of metallization in the chip.

Abstract translation: 一种用于在集成电路芯片30上通过使用镶嵌工艺，优选在芯片30中的铜金属化层32以及用于兼容性的球限制金属化中，优选地形成具有球限制金属化的Pb-铅C4连接或俘获垫37的方法。 在两个实施例中，捕获垫52形成在顶部绝缘层51中，并且还用作芯片中的最终金属化水平。

公开(公告)号：WO2008100923A3

公开(公告)日：2008-11-06

申请号：PCT/US2008053703

申请日：2008-02-12

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

IPC: B23K31/02 ,  H01L29/12

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/0501 ,  H01L2224/05083 ,  H01L2224/05546 ,  H01L2224/05624 ,  H01L2224/114 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/116 ,  H01L2224/11849 ,  H01L2224/11902 ,  H01L2224/13006 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A system and method for eliminating undercut when forming a C4 solder bump for BLM (Ball Limiting Metallurgy) and improving the C4 pitch. In the process, a barrier layer metal stack (20') is deposited above a metal pad layer (19'). A top layer (22') of the barrier layer metals (e.g., Cu) is patterned by CMP with a bottom conductive layer (21 ') of the barrier metal stack (20') removed by etching. The diffusion barrier (40) and C4 solder bump (50) may be formed by electroless plating, in one embodiment, using a maskless technique, or by an electroplating techniques using a patterned mask. This allows the pitch of the C4 solder bumps to be reduced.

Abstract translation: 一种用于在形成用于BLM（限流冶金）的C4焊料凸块并提高C4间距时消除底切的系统和方法。 在该过程中，在金属垫层（19'）上方沉积阻挡层金属叠层（20'）。 通过CMP对阻挡层金属（例如Cu）的顶层（22'）进行图案化，通过蚀刻去除阻挡金属叠层（20'）的底部导电层（21'）。 扩散阻挡层（40）和C4焊料凸块（50）可以通过化学镀，在一个实施例中使用无掩模技术，或通过使用图案化掩模的电镀技术形成。 这样可以减少C4焊料凸点的间距。

公开(公告)号：WO2007146757A3

公开(公告)日：2008-03-20

申请号：PCT/US2007070661

申请日：2007-06-08

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  MUZZY CHRISTOPHER D ,  SAUTER WOLFGANG

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11912 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: In a first aspect, a method comprises depositing a first metal containing layer (16) into a trench structure, which contacts a metalized area (12) of a semiconductor structure (10). The method further includes patterning at least one opening in a resist to the first metal containing layer (16). The opening should be in alignment with the trench structure. At least a pad metal containing layer (20) is formed within the at least one opening (preferably by electroplating processes). The resist (18) and the first metal layer (16) underlying the resist (18) are then etched (with the second metal layer (20) acting as a mask, in embodiments). The method includes flowing solder material (22) within the trench and on pad metal containing layer (20) after the etching process. The structure is a controlled collapse chip connection (C4) structure comprising at least one electroplated metal layer formed in a resist pattern to form at least one ball limiting metallurgical layer. The structure further includes an underlying metal layer devoid of undercuts.

Abstract translation: 在第一方面，一种方法包括将第一含金属层（16）沉积到与半导体结构（10）的金属化区域（12）接触的沟槽结构中。 该方法还包括将抗蚀剂中的至少一个开口构图到第一含金属层（16）。 开口应与沟槽结构对齐。 在至少一个开口内（优选地，通过电镀工艺）形成至少一块垫金属层（20）。 然后在实施例中蚀刻抗蚀剂（18）和抗蚀剂（18）下面的第一金属层（16）（第二金属层（20）用作掩模）。 该方法包括在蚀刻工艺之后使沟槽内的焊料材料（22）和衬垫金属含有层（20）流动。 该结构是受控的崩溃芯片连接（C4）结构，包括至少一个以抗蚀剂图形形成的电镀金属层，以形成至少一个球限制冶金层。 该结构还包括没有底切的底层金属层。

公开(公告)号：DE60011837D1

公开(公告)日：2004-08-05

申请号：DE60011837

申请日：2000-04-04

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  MOTSIFF WILLIAM T

IPC: H01L21/82 ,  H01L23/52 ,  H01L21/3205 ,  H01L23/525

Abstract: A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy. Fabrication methods for providing overlaying material to the entire fuse link line, or to selective portions of the fuse link line are presented.

公开(公告)号：DE60011837T2

公开(公告)日：2005-08-25

申请号：DE60011837

申请日：2000-04-04

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  MOTSIFF WILLIAM T

IPC: H01L21/82 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525

Abstract: A high laser absorption copper fuse can minimize the laser energy needed to delete the fuse portion of the conductor. Significantly, this type of fuse structure would allow for formation of copper fuses that can be deleted with appreciably less incident energy, mainly by increasing the absorption of the fuse link at the given incident laser energies. A metal wiring line contains a fuse link segment wherein the fuse link segment is composed of a stack of at least two metals. The underlayer material in the stack of metals is the primary electrical copper conductor, and the overlayer metal, also an electrical conductor, primarily tungsten or titanium-tungsten in composition, has predetermined thickness and optical properties chosen such that the combination of the overlayer metal with the underlayer metal provides for high absorption characteristics to incident infrared energy. Fabrication methods for providing overlaying material to the entire fuse link line, or to selective portions of the fuse link line are presented.

公开(公告)号：WO2007084907A8

公开(公告)日：2009-01-29

申请号：PCT/US2007060615

申请日：2007-01-17

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  LANDERS WILLIAM F ,  ZUPANSKI-NIELSEN DONNA S

Inventor： DAUBENSPECK TIMOTHY H ,  LANDERS WILLIAM F ,  ZUPANSKI-NIELSEN DONNA S

IPC: H01L21/44

CPC classification number: H01L21/288 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05575 ,  H01L2224/05599 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/01015

Abstract: The present invention relates to a method for fabricating a semiconductor device with a last level copper-to-C4 connection that is essentially free of aluminum. Specifically, the last level copper-to-C4 connection comprises an interfacial cap structure (30) containing CoWP, NiMoP, NiMoB, NiReP, NiWP, and combinations thereof. Preferably, the interfacial cap structure comprises at least one CoWP layer. Such a CoWP layer can be readily formed over a last level copper interconnect (22) by a selective electroless plating process.

Abstract translation: 本发明涉及一种用于制造具有基本上不含铝的最后一级铜对C4连接的半导体器件的方法。 具体地说，最后一级的铜对C4连接包括含有CoWP，NiMoP，NiMoB，NiReP，NiWP及其组合的界面帽结构（30）。 优选地，界面帽结构包括至少一个CoWP层。 这种CoWP层可以通过选择性无电镀方法容易地在最后一级的铜互连（22）上形成。