公开(公告)号：EP1687850A4

公开(公告)日：2008-06-25

申请号：EP04779326

申请日：2004-07-28

Applicant: IBM

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

IPC: H01L23/28 ,  H01L20060101 ,  H01L21/301 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/78 ,  H01L23/00 ,  H01L23/58

CPC classification number: H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A crack stop (28) for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal (12) is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

公开(公告)号：JPS62160743A

公开(公告)日：1987-07-16

申请号：JP195287

申请日：1987-01-09

Applicant: INTEL CORP ,  IBM

Inventor： CHAMBERS STEPHEN T ,  LUCE STEPHEN E

IPC: H01L21/28 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768

公开(公告)号：WO2005013330A2

公开(公告)日：2005-02-10

申请号：PCT/US2004024228

申请日：2004-07-28

Applicant: IBM ,  DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

Inventor： DAUBENSPECK TIMOTHY H ,  GAMBINO JEFFREY P ,  LUCE STEPHEN E ,  MCDEVITT THOMAS J ,  MOTSIFF WILLIAM T ,  POULIOT MARK J ,  ROBBINS JENNIFER C

IPC: H01L20060101 ,  H01L21/301 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/78 ,  H01L23/00 ,  H01L23/28 ,  H01L23/58 ,  H01L

CPC classification number: H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A crack stop (28) for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal (12) is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

Abstract translation: 使用金属互连在集成电路（IC）上形成集成电路（IC）的低K电介质材料的裂缝阻挡（28），所述金属互连在低K电介质中不形成自钝化氧化物层（例如铜或银互连） 材料以防止在切割操作期间由于沿着IC芯片的外围边缘形成的碎裂和破裂而导致对IC芯片的有源区域的损坏。 防潮层或边缘密封件（12）形成为沿着IC芯片的有效区域的外周边缘定位的金属堆叠。 通过位于IC芯片的外周上的防潮/边缘密封件外侧的至少一个沟槽或槽来形成止裂件。

公开(公告)号：GB2510755A

公开(公告)日：2014-08-13

申请号：GB201408506

申请日：2012-10-03

Applicant: IBM

Inventor： LUCE STEPHEN E ,  STAMPER ANTHONY K

IPC: H03H3/02

Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS processes, methods of manufacture and design structures are disclosed. The method includes forming at least one beam (44) comprising amorphous silicon material (29) and providing an insulator material (32) over and adjacent to the amorphous silicon beam. The method further includes forming a via (50) through the insulator material and exposing a material (25) underlying the amorphous silicon beam (44). The method further includes providing a sacrificial material (36) in the via and over the amorphous silicon beam. The method further includes providing a lid (38) on the sacrificial material and over the insulator material. The method further includes venting, through the lid (vent hole 40), the sacrificial material and the underlying material to form an upper cavity (42a) above the amorphous silicon beam and a lower cavity (42b) below the amorphous silicon beam, respectively.

公开(公告)号：DE3684298D1

公开(公告)日：1992-04-16

申请号：DE3684298

申请日：1986-12-09

Applicant: IBM

Inventor： CHAMBERS STEPHEN T ,  LUCE STEPHEN E

IPC: H01L21/28 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/60

Abstract: A method for forming contact openings (19) in semiconductor devices. A borosilicate glass layer (13) is deposited over the gate and drain area (14, 11) of a device, followed by a borophosphosilicate glass layer (15). After masking with photoresist (16) and defining openings (17) the borophosphosilicate glass (15) is isotropically etched to undercut the resist layer (16). A plasma etch is utilized to anisotropically etch the borosilicate glass layer (13) and expose the surface of the drain area (11). After the photoresist (16) is stripped away, a reflow step is employed to reduce the sharp edges of the glass layer and result in a sloped contact opening profile. Good metal coverage is achieved while maintaining isolation of the gate (14).

公开(公告)号：DE112012004340T5

公开(公告)日：2014-07-03

申请号：DE112012004340

申请日：2012-10-03

Applicant: IBM

Inventor： LUCE STEPHEN E ,  STAMPER ANTHONY K

IPC: B81C1/00

Abstract: Es werden akustische Bulk-Wellen-Filter und/oder akustische Bulk-Resonatoren, die mit CMOS-Einheiten kombiniert sind, Verfahren zur Herstellung sowie Entwurfsstrukturen bereitgestellt. Das Verfahren beinhaltet ein Bilden von wenigstens einem Träger (44), der ein Material (29) aus amorphem Silicium aufweist, sowie ein Bereitstellen eines Isolatormaterials (32) über und benachbart zu dem Träger aus amorphem Silicium. Das Verfahren beinhaltet des Weiteren ein Bilden eines Durchkontakts (50) durch das Isolatormaterial hindurch sowie ein Freilegen eines Materials (25), das unter dem Träger (44) aus amorphem Silicium liegt. Das Verfahren beinhaltet des Weiteren ein Bereitstellen eines Opfermaterials (36) in dem Durchkontakt und über dem Träger aus amorphem Silicium. Das Verfahren beinhaltet des Weiteren das Bereitstellten eine Kappe (38) auf dem Opfermaterial und über dem Isolatormaterial. Das Verfahren beinhaltet des Weiteren ein Abführen des Opfermaterials und des darunter liegenden Materials durch die Kappe (Öffnung 40 zum Abführen) hindurch, um einen oberen Hohlraum (42a) oberhalb des Trägers aus amorphem Silicium beziehungsweise einen unteren Hohlraum (42b) unterhalb des Trägers aus amorphem Silicium zu bilden.

公开(公告)号：SG63784A1

公开(公告)日：1999-03-30

申请号：SG1997004394

申请日：1997-12-10

Applicant: IBM

Inventor： HAKEY MARK C ,  HORAK DAVID V ,  LUCE STEPHEN E ,  MCDEVITT THOMAS L ,  NOBLE WANDELL P

IPC: H01L21/18 ,  H01L21/22 ,  H01L23/48

公开(公告)号：SG73615A1

公开(公告)日：2000-06-20

申请号：SG1999001011

申请日：1999-02-23

Applicant: IBM

Inventor： COONEY EDWARD C ,  LUCE STEPHEN E ,  COTE WILLIAM JOSEPH ,  GOLDBLATT RONALD D

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/283 ,  H01L21/98 ,  H01L23/52

公开(公告)号：DE69220393T2

公开(公告)日：1998-01-15

申请号：DE69220393

申请日：1992-02-04

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  DAUBENSPECK TIMOTHY H ,  LUCE STEPHEN E ,  POLEY DENIS J ,  PREVITI-KELLEY ROSEMARY A ,  VIENS GARY P ,  YOON JUNG H

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.

公开(公告)号：DE69220393D1

公开(公告)日：1997-07-24

申请号：DE69220393

申请日：1992-02-04

Applicant: IBM

Inventor： ABERNATHEY JOHN R ,  DAUBENSPECK TIMOTHY H ,  LUCE STEPHEN E ,  POLEY DENIS J ,  PREVITI-KELLEY ROSEMARY A ,  VIENS GARY P ,  YOON JUNG H

IPC: G03F7/11 ,  G03F7/09 ,  G03F7/36 ,  H01L21/027

Abstract: A process of patterning a conductive layer on a substrate avoiding webbing yet permitting high density patterning places two layers between the resist and the metal. The first layer is an antireflective coating such as titanium nitride applied to the metal. The second layer is a barrier comprising silicon such as sputtered silicon or SiO2. The barrier layer may also be a thin coating of spin-on glass. The barrier layer prevents interaction between the TiN and acid groups which are generated during exposure of the resist. With this structure in place the resist is applied, exposed and developed.