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公开(公告)号：AT304784T
公开(公告)日：2005-09-15
申请号：AT03720383
申请日：2003-03-10
Applicant: IBM
Inventor： ELEFTHERIOU EVANGELOS S , OELCER SEDAT , ABDELILAH YOUSSEF , DAVIS GORDON TAYLOR , DERBY JEFF H , HWANG DONGMING , WARE MALCOLM , YE HUA
Abstract: A method and systems for optimizing Asymmetric Digital Subscriber Line (ADSL) connections in DSL Access Multiplexor (DSLAM) that marries benefits of G.dmt and G.lite standards, using a flexible method implemented on a programmable Digital Signal Processor (DSP) and a Network Processor (NP) is disclosed. It provides a means to support full G.dmt rates for any of the attached users as long as less than half the users are actively moving data through the DSLAM, but by only using half the digital signal processing hardware and half the power consumption for the line drivers. The invention allows doubling the number of,ADSL ports available over a conventional scheme given about 20% more power is under 50% with only half the respective connections, all those G.dmt rates possible on their exceeds 50%, gradually active G.lite rates based on either based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates. budget. When the utilization subscribers active on their users experience the maximum wire. However, when utilization subscribers start to experience a fixed policy or one that is based on a tiered tariff structure, until ultimately, when the utilization reaches 100%, all subscribers will be forced back to a maximum rate afforded by G.lite. Only as utilization drops back off, will active subscribers be brought back up to G.dmt's maximum transmission rates. Once the utilization drops below 50% again, then all active subscribers will be able to utilize G.dmt's maximum transmission rates.
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公开(公告)号：DE69634870D1
公开(公告)日：2005-07-28
申请号：DE69634870
申请日：1996-10-28
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HARBOUR EDWARD EARL , LEPPERT PAUL , MARKS LAURENCE VICTOR , MINN ANDRE BYUNGYUP , STEVENS BRYAN S
Abstract: An adapter (250) for providing data communications for a personal computer to other remote data communications systems of various communication platforms is disclosed. The remote data communications systems can be a data circuit terminating equipment (DCE) such as a modem, or a data terminating equipment (DTE) such as an ISDN terminal adapter. The adapter comprises a programmable digital signal processing device (22), a memory device (24, 25) and an assortment of transceiving devices (27, 28). A software program is stored in the memory device for instructing the programmable digital signal processing device. The transceiving devices is controlled by the programmable DSP device such that the appropriate transceiving device can be activated for providing data communications, according to the type of communication platform utilized by the remote data communications equipment.
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公开(公告)号：CA2385339C
公开(公告)日：2005-06-28
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： JENKINS STEVEN KENNETH , SIEGEL MICHAEL STEVEN , CALVIGNAC JEAN LOUIS , BASS BRIAN MITCHELL , LEAVENS ROSS BOYD , VERPLANKEN FABRICE JEAN , HEDDES MARCO , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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公开(公告)号：DE10110504A1
公开(公告)日：2001-10-18
申请号：DE10110504
申请日：2001-03-03
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , VERPLANKEN FRABRICE JEAN
Abstract: The method involves providing several instruction execution threads as independent processes in a sequential time frame. The execution threads are arranged in a queue so that they have overlapping access to the accessible data. A first thread in the queue is executed, and the execution control is transferred to the next thread in the queue when an event occurs that blocks the execution of the first thread. Independent claims are included for a processing system, a method of executing several independent threads in a processor, the use of a prefetch buffers in connection with a number of independent instruction threads, and for a thread execution controller.
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公开(公告)号：CA2385339A1
公开(公告)日：2001-07-12
申请号：CA2385339
申请日：2000-12-21
Applicant: IBM
Inventor： HEDDES MARCO , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , DAVIS GORDON TAYLOR , BASS BRIAN MITCHELL , VERPLANKEN FABRICE JEAN , CALVIGNAC JEAN LOUIS , JENKINS STEVEN KENNETH
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristic s for the frame (or input information unit) include the type of layer 3 protoc ol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics o f the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction addre ss and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed a nd forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：DE3066868D1
公开(公告)日：1984-04-12
申请号：DE3066868
申请日：1980-11-14
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR
IPC: G06F7/00 , G06F9/22 , H03K19/173 , H03K19/177 , H03K19/20
Abstract: A programmable sequential logic array mechanism is provided for performing logical operations and solving logical equations. The mechanism includes a search array subsystem (1) for receiving a plurality of binary input signals via input lines (2). The search array subsystem includes an addressable storage array (3) for supplying input control words for testing for different input signal conditions. The sequential logic array mechanism also includes a read array subsystem (13) for producing a plurality of binary output signals on output lines (14). This read array subsystem includes an addressable storage array (15) for supplying output signal control words. The results of the tests performed by the search array subsystem are used to select which one of the output signal control words are allowed to establish or change the read array output signals.
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公开(公告)号：DE10110504B4
公开(公告)日：2006-11-23
申请号：DE10110504
申请日：2001-03-03
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , VERPLANKEN FRABRICE JEAN
Abstract: A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
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公开(公告)号：ES2226958T3
公开(公告)日：2005-04-01
申请号：ES00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH
Abstract: Un aparato que comprende: un substrato semiconductor; N unidades (110) de procesamiento fabricadas sobre el substrato, donde N > 1; una primera memoria de datos interna accesible para dichas N unidades de procesamiento; una unidad (112) de expedición acoplada operativamente a las N unidades de procesamiento para recibir y transmitir una unidad de información de entrada a una de las N unidades de procesamiento; una unidad (118) de clasificación acoplada a la unidad (112) de expedición, incluyendo dicha unidad de clasificación una unidad (114) de comparación para determinar un formato de datos para una unidad de información de entrada y para generar y almacenar en la memoria de datos interna indicadores de salida para la unidad de información de entrada, que indican el formato de datos de la unidad de información de entrada y una dirección de arranque para la unidad de información de entrada, cuyos indicadores y dirección de arranque están disponibles para una de las N unidades de procesamiento durante su procesamiento de la unidad de información de entrada y son utilizados en el procesamiento de la unidad de información de entrada; y una unidad (114) de compleción soportada en el substrato semiconductor y conectada operativamente a las N unidades (110) de procesamiento para recibir la unidad de información procesada por la unidad considerada de las N unidades (110) de procesamiento.
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公开(公告)号：DE69633601D1
公开(公告)日：2004-11-18
申请号：DE69633601
申请日：1996-08-09
Applicant: IBM
Inventor： ANDREWS LAWRENCE PAUL , DAVIS GORDON TAYLOR , JOHNSON WILLIE JAMES , JONES JR , LANDA ROBERT EUGENE , MANDALIA BAIJU DHIRAJLAL , SINIBALDI JOHN CLAUDE
Abstract: In an communication system including a computer system comprising a digital signal processing adapter for performing a set of tasks, and a E-1 port for providing and receiving time division multiplexed (TDM) signals in accordance with a first inter-system communication protocol, such as the E-1 or T-1 protocols, a communication subsystem, for coupling to the IP system. The communication subsystem includes an E-1 link for coupling to the first I/O port, and for providing and receiving TDM signals in accordance with the E-1 or T-1 protocols. The subsystem further includes a digital signal processor adapter, coupled to the second I/O port, for enhancing processing capability of the digital signal processing resource; and a third I/O port, coupled to the digital signal processor circuit, for providing and receiving signals in accordance with the first or a second inter-system communication protocol.
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公开(公告)号：GB2366426A
公开(公告)日：2002-03-06
申请号：GB0108828
申请日：2001-04-09
Applicant: IBM
Inventor： DAVIS GORDON TAYLOR , HEDDES MARCO C , LEAVENS ROSS BOYD , RINALDI MARK A
Abstract: A processor system comprises a core language processor 101, co-processors 107 - 111; each having special purpose, scalar 116 and array 117, registers; and an interface between the processors, where the interface maps the special purpose registers into a common address map. The system may be utilised as a protocol processor unit to provide instruction communication to a network, and the co-processors may compute CRC checksums, move data between local and main memories, search a tree structure, enqueue packets or assist in accessing the contents of registers. The interface may take the form of an execution interface 106 or a data interface 130.
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