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    TASK MANAGEMENT APPARATUS
    13.
    发明专利
    TASK MANAGEMENT APPARATUS 未知

    公开(公告)号：CA1084628A

    公开(公告)日：1980-08-26

    申请号：CA281861

    申请日：1977-06-30

    Applicant: IBM

    Inventor： DAVIS MICHAEL I

    IPC: G06F9/19 ,  G06F9/20

    Abstract: TASK MANAGEMENT APPARATUS A data processing system is described which has multiple sets of registers each of which is capable of autonomously controlling a common storage and common arithmetic and logic control circuits to execute respective tasks of a program. Level status blocks (LSBs), each assigned to a respective task, are held in main storage; and each contains such address and status data as is required for task execution in a controlled environment. Apparatus, including a current level register, a selected level register, a pending level register and an in-process bit latch, is controlled during the execution of a load level status block (LLSB) instruction to transfer the LSB of a selected task from storage to the selected register set, determine the status of the in-process bit of the selected task LSB and the relative priority levels of the current and selected tasks, and pursuant to said two determinations handle the task dispatching, preemption, enqueuing, dequeuing functions without the need for further software processing. At the completion of the LLSB instruction execution, either the current task execution is continued, the selected task is initiated, a pending task is initiated or a system wait state is entered. A store level status block (STLSB) instruction is executed to copy the LSB of a selected task from the register set to storage. Hardware backup registers are provided to hold certain updated status of the current register set to improved performance. These backup registers are changed during the LLSB execution if task switching occurs and are restored to the current register set during STLSB execution.

    KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM
    14.
    发明专利
    KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM 未知

    公开(公告)号：CA1081859A

    公开(公告)日：1980-07-15

    申请号：CA275573

    申请日：1977-04-05

    Applicant: IBM

    Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I ,  HOOD ROBERT A ,  GRAYBIEL LYNN A ,  KAHN SAMUEL ,  OSBORNE WILLIAM S

    IPC: G06F12/14 ,  G06F12/02 ,  G06F9/20

    Abstract: KEY CONTROLLED ADDRESS RELOCATION TRANSLATION SYSTEM Translates each active address key (AAK) into a respective addressability in physical main memory. Each addressability comprises one or more physical blocks which may be scattered in the main memory. Address keys are contained in plural key register sections, and AAK select circuits outgate to the translator each M K from a key register section corresponding to the access type for each storage access request currently received from a processor or I/O channel. Each address key identifies a particular stack of one or more segmentation registers. Each segmentation register can be assigned the address of any segment (i.e. a block of contiguous physical addresses located anywhere in the main memory). Each segmentation register also has validity and read-only flag bits for its assigned block. Each stack can translate a contiguous set of logical program addresses into physical addresses. Any stack can support all logical addresses apparent to a program, although the machine can cause a single program to access plural addressabilities due to the machine assignment of address keys. For each storage access request for a logical program address, a stack is addressed by the AAK to determine an addressability. Then a register in the stack is addressed by high-order bits in the logical program address. The addressed register outputs the translated block address. The main memory can have any physical size in relation to the number of stacks, and to the number of segmentation registers in each stack.

    NON-TRANSLATABLE STORAGE PROTECTION CONTROL SYSTEM
    15.
    发明专利
    NON-TRANSLATABLE STORAGE PROTECTION CONTROL SYSTEM 未知

    公开(公告)号：CA1075367A

    公开(公告)日：1980-04-08

    申请号：CA275544

    申请日：1977-04-05

    Applicant: IBM

    Inventor： BIRNEY RICHARD E ,  DAVIS MICHAEL I

    IPC: G06F11/00 ,  G06F12/14 ,  G06F21/24 ,  G06F13/00

    Abstract: Combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in main memory. This combination can provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses. Special features include a shared protect key, which need not be loaded in the AKR, to make specified sub-range(s) shareable by all users of the system, so that any user can access the blocks in memory associated with the shared protect key. For I/O accesses, an override is provided which ignores any read-only control of any memory block to which an I/O access is requested. Supervisor accesses can be made in all key areas, regardless of the AAK, the protect keys, or the read-only flag bits.

    16.
    发明专利
    未知

    公开(公告)号：FR2376460A1

    公开(公告)日：1978-07-28

    申请号：FR7735664

    申请日：1977-11-18

    Applicant: IBM

    Inventor： DAVIS MICHAEL I ,  HOOD ROBERT A ,  MAYES GARY W

    IPC: G06F9/305 ,  G06F9/34 ,  G06F12/04 ,  G06F9/06 ,  G06F7/38

    Abstract: A method of accessing variable-length bit fields in the memory of an electronic data processing system irrespective of the relationship between the boundaries of addressable elements within said memory and the start and end of the bit fields comprising the operations of: setting the initial values of a base register within said system to contain a representation of a base address of an addressable element; setting the initial values of a shift register within said system to contain a representation of the offset in said memory of the beginning of a particular bit field from said base address; combining the contents of said base and offset registers in such a way as to provide a representation of the position in said memory of the first bit of said particular bit field; create a single instruction that contains a representation of the length of said particular bit field. (Machine-translation by Google Translate, not legally binding)

    GRAPHICS DISPLAY TERMINAL AND METHOD OF STORING ALPHANUMERIC DATA THEREIN
    18.
    发明专利
    GRAPHICS DISPLAY TERMINAL AND METHOD OF STORING ALPHANUMERIC DATA THEREIN 未知

    公开(公告)号：CA1241780A

    公开(公告)日：1988-09-06

    申请号：CA483259

    申请日：1985-06-05

    Applicant: IBM

    Inventor： BOWATER RONALD J ,  DAVIS MICHAEL I ,  FARR ROBERT W E ,  POWELL COLIN V

    IPC: G06G7/163 ,  G09G5/06 ,  G09G3/00

    Abstract: The specification describes a method of storing alphanumeric characters (including special symbols) in a graphics display terminal comprising a raster-scan display device and a refresh buffer including a plurality of bit planes (1 to 6) each having a respective bit storage location corresponding to each addressible pel position on the screen of the display device. In the method, a first bit plane (luminance plane 1) stores high resolution luminance data defining alphanumeric characters each as a selection of "on" bits within a respective n x m array (character box) where n is the width of the character box in the scan line direction, and at least one further bit plane (attribute plane 2) stores low resolution colour data for the characters. The attribute plane (2) comprises a respective n-bit set of storage locations which corresponds to each n-bit wide by one pel deep portion of a character box in the luminance plane (1) and defines at least the colour and/or intensity of the foreground and background of the character for the width of the character box in respect of a single scan line. The specification also describes a graphics display terminal in which data in the luminance and attribute planes may be selectively decoded either as alphanumeric data stored as above, or as bit-mapped graphics data.

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