公开(公告)号：DE69620528T2

公开(公告)日：2003-01-23

申请号：DE69620528

申请日：1996-09-16

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G01R31/28 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/50 ,  G11C29/00

公开(公告)号：DE69431867D1

公开(公告)日：2003-01-23

申请号：DE69431867

申请日：1994-10-07

Applicant: IBM

Inventor： BRONNER GARY BELA ,  KENNEY DONALD MCALPINE ,  DEBROSSE JOHN KENNETH

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：DE69620528D1

公开(公告)日：2002-05-16

申请号：DE69620528

申请日：1996-09-16

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  KIRIHATA TOSHIAKI ,  WONG HING

IPC: G01R31/28 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4094 ,  G11C29/50 ,  G11C29/00

公开(公告)号：DE69526006D1

公开(公告)日：2002-05-02

申请号：DE69526006

申请日：1995-07-13

Applicant: IBM

Inventor： DEBROSSE JOHN KENNETH ,  LARY JENIFER EDITH ,  SPROGIS EDMUND JURIS

IPC: H01L21/822 ,  G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  G11C7/00

Abstract: An interconnection array layout and method are provided for a plurality of paired line conductors of a given length extending principally parallel. A single crossing region traverses the paired line conductors intermediate the given length, wherein the line conductors of each pair of line conductors cross such that inter-pair capacitive coupling is matched. Intra-pair capacitive coupling is avoided by separating the line conductors of each pair of line conductors by two pitches and disposing therebetween a line conductor of a different pair of line conductors. Applications include semiconductor memory arrays, such as DRAM structures, and address/data busses wherein paired true/complement line conductors are employed.

公开(公告)号：SG43376A1

公开(公告)日：1997-10-17

申请号：SG1996010140

申请日：1996-06-24

Applicant: IBM

Inventor： CRONIN JOHN EDWARD ,  DEBROSSE JOHN KENNETH ,  WONG HING

IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/768 ,  H01L27/00

Abstract: An improved method for isolating electrical conductors which are positioned over each other is disclosed. These conductors would normally contact each other because of the somewhat imprecise patterning and etching steps used to fabricate a multitude of conductive elements, e.g., in a very dense semiconductor structure. The method involves forming a recess in the upper surface of the lower conductor, and then at least partially filling the recess with an oxide-type material. This method is particularly valuable in the construction of stacked capacitor cells. Cells prepared using this technique also form part of this invention.