公开(公告)号：BR9105317A

公开(公告)日：1992-08-25

申请号：BR9105317

申请日：1991-12-10

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  SUAREZ GUSTAVO A ,  WILKIE BRUCE J

IPC: G06F13/10 ,  G06F3/14 ,  G09G1/16 ,  G09G5/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  H04N5/222 ,  H04N5/265 ,  G06F13/00

Abstract: An information handling apparatus for transferring and composing image signals for display. The apparatus includes a bus adapted to allow selective access for multiple independent image signals generated by respective independent image sources. The selective access enables composition of the independent image signals in response to control information; the composition enables real time display of a composed image signal.

公开(公告)号：BR9105311A

公开(公告)日：1992-08-25

申请号：BR9105311

申请日：1991-12-10

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  SUAREZ GUSTAVO A ,  WILKIE BRUCE J

IPC: G06F3/14 ,  G06T1/00 ,  G06T3/00 ,  G06T11/80 ,  G09G1/16 ,  G09G5/00 ,  G09G5/14 ,  H04H60/04 ,  H04N5/262 ,  G06F15/66

Abstract: An information handling apparatus for transferring and composing image signals including a plurality of media sources configured to provide a corresponding plurality of image signals, a media bus connected to the media sources, and a media control module coupled to the media bus. The media bus allows selective access for the plurality of image signals. The selective access enables composition of the independent image signals in response to control information. The media control module receives a composed image signal from the media bus and to provides the composed image signal to a display device.

公开(公告)号：CA2055554A1

公开(公告)日：1992-06-12

申请号：CA2055554

申请日：1991-11-14

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  SUAREZ GUSTAVO A ,  WILKIE BRUCE J

IPC: G06F3/14 ,  G06T1/00 ,  G06T3/00 ,  G06T11/80 ,  G09G1/16 ,  G09G5/00 ,  G09G5/14 ,  H04H60/04 ,  H04N5/262 ,  G06F15/20 ,  G06F3/00 ,  H04L29/06 ,  H04N7/14

Abstract: An information handling apparatus for transferring and composing image signals including a plurality of media sources configured to provide a corresponding plurality of image signals, a media bus connected to the media sources, and a media control module coupled to the media bus. The media bus allows selective access for the plurality of image signals. The selective access enables composition of the independent image signals in response to control information. The media control module receives a composed image signal from the media bus and to provides the composed image signal to a display device.

公开(公告)号：BR9002304A

公开(公告)日：1991-08-06

申请号：BR9002304

申请日：1990-05-17

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  BAKER ERNEST D ,  SUAREZ GUSTAVO A

IPC: G06F9/46 ,  G06F9/50 ,  G06F11/16 ,  G06F12/02 ,  G06F13/18 ,  G06F15/16 ,  G06F15/167 ,  G06F15/177 ,  G06F13/14

Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors dirertly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

公开(公告)号：BR9002280A

公开(公告)日：1991-08-06

申请号：BR9002280

申请日：1990-05-16

Applicant: IBM

Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN MARIO ,  SANDERSON KENNETH R

IPC: G06F15/16 ,  G06F9/46 ,  G06F11/00 ,  G06F11/16 ,  G06F11/20 ,  G06F12/02 ,  G06F13/368 ,  G06F15/177 ,  G06F13/00

Abstract: The functions of two virtual operating systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

公开(公告)号：CA1149070A

公开(公告)日：1983-06-28

申请号：CA352402

申请日：1980-05-21

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR

IPC: G06F13/28 ,  G06F3/00 ,  G06F3/06 ,  G06F9/06 ,  G06F9/26 ,  G06F11/34 ,  G06F13/00

Abstract: A flexible and versatile high performance input/output (I/O) controller for transferring data between a host processor and one or more I/O units. One feature for improving performance is the provision of an interleaving mechanism for interleaving two different modes of data transfer between the host processor and the I/O controller. One mode is the cycle stealing of data between the I/O controller and the main storage unit of the host processor with such cycle stealing being controlled by the I/O controller. The other mode is an I/O command type of data transfer mode which is under the control of the host processor and wherein for each word of data transferred the host processor supplies an I/O command and an I/O address to the I/O controller.

公开(公告)号：CA1148265A

公开(公告)日：1983-06-14

申请号：CA352373

申请日：1980-05-21

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  JACKSON TIMOTHY ,  ZIPOY WILLIAM L

IPC: G06F13/28 ,  G06F3/00 ,  G06F3/06 ,  G06F9/22 ,  G06F9/26 ,  G06F9/46 ,  G06F11/34 ,  G06F13/00

Abstract: HIGH PERFORMANCE I/O CONTROLLER FOR TRANSFERRING DATA BETWEEN A HOST PROCESSOR AND MULTIPLE I/O UNITS An I/O controller for transferring data between a host processor and an I/O unit is disclosed comprising: a random access storage unit located in the I/O controller for storing data; first selectively operable data transfer circuitry for providing a data transfer path between the host processor and the controller storage unit; second selectively operable data transfer circuitry for providing a data transfer path between the controller storage unit and the I/O unit; first storage accessing circuitry for supplying addresses to the controller storage unit and selection signals to the second data transfer circuitry for enabling the transfer of data between the controller storage unit and the I/O unit; second storage accessing circuitry for supplying host processor main storage addresses to the host processor, controller storage addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data between the host processor main storage unit and the controller storage unit in a first data transfer mode; third storage accessing circuitry responsive to addresses received from the host processor for supplying addresses to the controller storage unit and selection signals to the first data transfer circuitry for enabling the transfer of data between the host processor and the controller storage unit in a second data transfer mode; and interleaving control circuitry for enabling the second mode data transfers to be interleaved with the first mode data transfers.

公开(公告)号：BR9002305A

公开(公告)日：2005-02-01

申请号：BR9002305

申请日：1990-05-17

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  JOYCE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R ,  BAKER ERNEST D

IPC: G06F15/16 ,  G06F9/46 ,  G06F15/17 ,  G06F15/173 ,  G06F15/177 ,  G06F13/14

Abstract: The functions of two virtual opening systems (e.g. S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated form 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors across the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/88 and S/370 peer processor pairs to execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

公开(公告)号：CA2009779C

公开(公告)日：1994-05-03

申请号：CA2009779

申请日：1990-02-07

Applicant: IBM

Inventor： BAKER ERNEST D ,  DINWIDDIE JOHN M JR ,  GRICE LONNIE E ,  JOYCE JAMES M ,  LOFFREDO JOHN M ,  SANDERSON KENNETH R

IPC: G06F15/16 ,  G06F9/46 ,  G06F11/00 ,  G06F11/16 ,  G06F11/20 ,  G06F12/02 ,  G06F13/368 ,  G06F15/177 ,  G06F9/06 ,  G06F12/00

Abstract: The functions of two virtual operating systems (e.g., S/370 VM, VSE or IX370 and S/88 OS) are merged into one physical system. Partner pairs of S/88 processors run the S/88 OS and handle the fault tolerant and single system image aspects of the system. One or more partner pairs of S/370 processors are coupled to corresponding S/88 processors directly and through the S/88 bus. Each S/370 processor is allocated from 1 to 16 megabytes of contiguous storage from the S/88 main storage. Each S/370 virtual operating system thinks its memory allocation starts at address 0, and it manages its memory through normal S/370 dynamic memory allocation and paging techniques. The S/370 is limit checked to prevent the S/370 from accessing S/88 memory space. The S/88 Operating System is the master over all system hardware and I/O devices. The S/88 processors access the S/370 address space in direct response to a S/88 application program so that the S/88 may move I/O data into the S/370 I/O buffers and process the S/370 I/O operations. The S/83 and S/370 peer processor pairs execute their respective Operating Systems in a single system environment without significant rewriting of either operating system. Neither operating system is aware of the other operating system nor the other processor pairs.

公开(公告)号：BR9200321A

公开(公告)日：1992-10-13

申请号：BR9200321

申请日：1992-01-31

Applicant: IBM

Inventor： DINWIDDIE JOHN M JR ,  FREEMAN BOBBY J ,  MICALLEF THOMAS J ,  SUAREZ GUSTAVO A ,  WILKIE BRUCE J

IPC: G09G5/00 ,  G06F3/14 ,  G06T3/00 ,  G09G5/14 ,  H04N5/765 ,  G06F15/62 ,  G06K9/36

Abstract: A multimedia solution is presented which allows a multimedia architecture to be implemented on an existing computer system. According to the invention, an expansion unit which incorporates a multimedia architecture is provided. The expansion unit is connected to an existing computer system via an expansion slot of an I/O bus of the existing computer as well as via a display device output terminal of the computer. The expansion unit is also connected to a display device. Accordingly, the expansion unit controls the presentation which is provided on the display device.