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    11.
    发明专利
    未知

    公开(公告)号：FR2315804A1

    公开(公告)日：1977-01-21

    申请号：FR7613470

    申请日：1976-04-29

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  ROBBINS GORDON J

    IPC: H01L21/822 ,  H01L21/331 ,  H01L21/82 ,  H01L27/04 ,  H01L27/118 ,  H01L29/73 ,  H03K19/173 ,  H03K19/08 ,  H01L27/06

    Abstract: A semiconductor chip layout including a plurality of logic cells arranged in columns. A cell may encompass one of two different magnitudes of area in the chip; and each column contains only cells having the same area. The layout is particularly appropriate for level sensitive logic systems which utilize both combinatorial as well as sequential networks. The combinatorial (combinational) networks are less orderly and require a greater number of selectable input connections, hence more area, than the sequential circuits. The wide and narrow columnar architecture allows a much greater circuit packing density on a chip, resulting in a substantial increase in the number of circuits for a given chip area. Performance is also increased because of the reduced area required by the sequential circuits.

    LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM
    12.
    发明专利
    LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM 未知

    公开(公告)号：CA1089031A

    公开(公告)日：1980-11-04

    申请号：CA280452

    申请日：1977-06-13

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTHER RONALD G ,  WILLIAMS THOMAS W

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F7/38

    Abstract: LEVEL SENSITIVE EMBEDDED ARRAY LOGIC SYSTEM A generalized and modular logic system is described for all arithmetic/logical units and their associated control storage and any other arrays. The logic system is partitioned into sections formed of combinational logic networks, storage circuitry, and arrays. The storage circuitry is sequential in operation and employs clocked dc latches. Two or more synchronous, non-overlapping, independent system clock trains are used to control the latches. The array is a rectangular array of storage element, M x N where, M is the number of words in the array and N is the number of bits in each word. The array may be read only, or it may be a read/write array. The array may be a programmable logic array (PLA). A single- sided delay dependency is imparted to the system. The feedback connections from the respective latch circuitry are made through combinational logic or an array to other latch circuitry. The clocking of the latches and of the array, if any, are such that the network may be operated in a race free mode. With each latch, there is provided additional circuitry so that each latch acts as one position of a shift register having input/output and shift controls that are independent of the system clocks and the system input/outputs. All of the shift register latches are coupled together into a single shift register. The logic between the latch inputs and the array inputs has the property that a 1 to 1 correspondences can exist between array inputs and the latch inputs. Furthermore, all of the array outputs are uniquely detectable at the latch or primary outputs.

    TESTING EMBEDDED ARRAYS
    13.
    发明专利
    TESTING EMBEDDED ARRAYS 未知

    公开(公告)号：CA1038079A

    公开(公告)日：1978-09-05

    申请号：CA239237

    申请日：1975-11-04

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B

    IPC: G11C29/00 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/02 ,  G11C29/12 ,  G11C29/20 ,  G01R15/12

    Abstract: TESTING EMBEDDED ARRAYS An LSI semiconductor device includes a memory array incorporating address and data registers, and associated combinatorial and or sequential logic circuitry. The array is "embedded" in the sense that the memory array is not directly accessible, either in whole or in part, from the input and output terminals or pads of the device. To facilitate testing, the address registers and data registers are converted to counters by the addition of an EXCLUSIVE OR circuit to two or more positions of the register. The address and data registers are stepped through all of their states. The data register counter outputs may then be compared with the array outputs, thereby allowing one to check address selection as well as the ability to write or read at each of the storage locations.

    14.
    发明专利
    未知

    公开(公告)号：FR2357005A1

    公开(公告)日：1978-01-27

    申请号：FR7716057

    申请日：1977-05-18

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  WILLIAMS THOMAS W

    IPC: G06F7/00 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/06

    Abstract: The disclosure relates to LSSD systems for use in digital computers and the like. More particularly, to an organization of logic in such systems to render the clock networks testable with minimal overhead. The advantages of the practice of the invention are particularly apparent and enhanced when the invention is employed in a Level Sensitive Scan Design (LSSD) System generally of the type disclosed in U.S. Pat. No. 3,783,254 and U.S. patent application Ser. No. 701,052, filed June 30, 1976.

    15.
    发明专利
    未知

    公开(公告)号：FR2356997A1

    公开(公告)日：1978-01-27

    申请号：FR7716797

    申请日：1977-05-26

    Applicant: IBM

    Inventor： EICHELBERGER EDWARD B ,  MUEHLDORF EUGEN I ,  WALTER RONALD G ,  WILLIAMS THOMAS W

    IPC: G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/319 ,  G06F1/10 ,  G06F7/00 ,  G06F7/57 ,  G06F17/50 ,  G11C19/00 ,  H03K3/037 ,  H03K19/00 ,  H03K19/08 ,  H03K19/20 ,  G06F1/04

    Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.

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