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公开(公告)号：DE10310081A1
公开(公告)日：2003-09-25
申请号：DE10310081
申请日：2003-03-07
Applicant: INFINEON TECHNOLOGIES AG , IBM
Inventor： FIFIELD JOHN A , HOKENMAIER WOLFGANG
IPC: H03K19/00 , H03K19/003
Abstract: A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.
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公开(公告)号：CA2002362A1
公开(公告)日：1990-09-10
申请号：CA2002362
申请日：1989-11-07
Applicant: IBM
Inventor： BLAKE ROBERT M , BOSSEN DOUGLAS C , CHEN CHIN L , FIFIELD JOHN A , KALTER HOWARD L , LO TIN C
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE60027065D1
公开(公告)日：2006-05-18
申请号：DE60027065
申请日：2000-01-21
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor： CHU ALBERT M , FIFIELD JOHN A , ROTELLA JASON E , DORTU JEAN-MARC
Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.
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公开(公告)号：AU2003304110A1
公开(公告)日：2004-11-26
申请号：AU2003304110
申请日：2003-04-30
Applicant: IBM
Inventor： TONTI WILLIAM R , BERRY WAYNE S , FIFIELD JOHN A , GUTHRIE WILLIAM H , KONTRA RICHARD S
IPC: H01L23/525 , H01L29/00 , H01L21/44
Abstract: A programmable device includes a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having first and second ends, and an upper surface S; the first end (12a) is substantially wider than the second end (12b), and a metallic material is disposed on the upper surface; the metallic material being physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and the metallic material.
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Patent Agency Ranking
公开(公告)号：CA2034027C
公开(公告)日：1995-12-19
申请号：CA2034027
申请日：1991-01-11
Applicant: IBM
Inventor： BARTH JOHN E JR , DRAKE CHARLES E , FIFIELD JOHN A , HOVIS WILLIAM P , KALTER HOWARD L , LEWIS SCOTT C , NICKEL DANIEL J , STAPPER CHARLES H , YANKOSKY JAMES A
IPC: G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42 , G11C7/00
Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by-carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：DE60027065T2
公开(公告)日：2006-10-05
申请号：DE60027065
申请日：2000-01-21
Applicant: IBM , INFINEON TECHNOLOGIES AG
Inventor： CHU ALBERT M , FIFIELD JOHN A , ROTELLA JASON E , DORTU JEAN-MARC
Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.
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公开(公告)号：CA2034027A1
公开(公告)日：1991-08-14
申请号：CA2034027
申请日：1991-01-11
Applicant: IBM
Inventor： BARTH JOHN E JR , DRAKE CHARLES E , FIFIELD JOHN A , HOVIS WILLIAM P , KALTER HOWARD L , LEWIS SCOTT C , NICKEL DANIEL J , STAPPER CHARLES H , YANKOSKY JAMES A
IPC: G11C11/401 , G06F11/10 , G11C29/00 , G11C29/42 , G11C7/00
Abstract: A DRAM having on-chip ECC (30) and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section (20), and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry (30) is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block (30) provides both the corrected data bits and the check bits to an SRAM (40). Thus, the check bits can be externally accessed, improving testability of the memory chip. At the same time, having a set of interrelated bits in the SRAM (40) improves access performance when using multi-bit access modes, which compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.
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公开(公告)号：CA2002362C
公开(公告)日：1994-02-01
申请号：CA2002362
申请日：1989-11-07
Applicant: IBM
Inventor： BLAKE ROBERT M , BOSSEN DOUGLAS C , CHEN CHIN L , FIFIELD JOHN A , KALTER HOWARD L , LO TIN C
Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH LOCK-UP FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：CA2002361C
公开(公告)日：1993-12-21
申请号：CA2002361
申请日：1989-11-07
Applicant: IBM
Inventor： BLAKE ROBERT M , BOSSEN DOUGLAS C , CHEN CHIN L , FIFIELD JOHN A , KALTER HOWARD L
Abstract: FAULT TOLERANT COMPUTER MEMORY SYSTEMS AND COMPONENTS EMPLOYING DUAL LEVEL ERROR CORRECTION AND DETECTION WITH DISABLEMENT FEATURE In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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