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    SEMICONDUCTOR BODY, DYNAMIC RANDOM ACCESS MEMORY, ELECTRIC ISOLATION, AND MANUFACTURE OF MEMORY CELL
    11.
    发明专利
    SEMICONDUCTOR BODY, DYNAMIC RANDOM ACCESS MEMORY, ELECTRIC ISOLATION, AND MANUFACTURE OF MEMORY CELL 失效

    公开(公告)号：JP2000228504A

    公开(公告)日：2000-08-15

    申请号：JP2000028340

    申请日：2000-02-04

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

    IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

    VERTICAL DRAM CELL HAVING WORD LINE SELF-ALIGNED WITH STORAGE TRENCH
    12.
    发明专利
    VERTICAL DRAM CELL HAVING WORD LINE SELF-ALIGNED WITH STORAGE TRENCH 失效

    公开(公告)号：JP2001085637A

    公开(公告)日：2001-03-30

    申请号：JP2000245911

    申请日：2000-08-14

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： FURUKAWA TOSHIHARU ,  GRUENING ULRIKE ,  HORAK DAVID V ,  MANDELMAN JACK A ,  RADENS CARL J ,  RUPP THOMAS S

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

    SEMICONDUCTOR DEVICE AND ITS FORMING METHOD
    13.
    发明专利
    SEMICONDUCTOR DEVICE AND ITS FORMING METHOD 失效

    公开(公告)号：JP2000277708A

    公开(公告)日：2000-10-06

    申请号：JP2000073717

    申请日：2000-03-16

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.

    DRAM STRUCTURE HAVING DEEP TRENCH BASE AND MANUFACTURING METHOD THEREFOR
    14.
    发明专利
    DRAM STRUCTURE HAVING DEEP TRENCH BASE AND MANUFACTURING METHOD THEREFOR 失效

    公开(公告)号：JP2000012801A

    公开(公告)日：2000-01-14

    申请号：JP14714699

    申请日：1999-05-26

    Applicant: IBM ,  SIEMENS AG

    Inventor： ECONOMIKOS LAERTIS ,  GRUENING ULRIKE ,  HO HERBERT L ,  RADENS CARL J ,  JAMMY RAGARAO ,  HOEPFNER JOACHIM ,  SHEN HUA

    IPC: H01L27/108 ,  H01L21/8242 ,  H01L27/10

    Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned collar and a buried plate while forming a reliable node dielectrics on the collar without requiring a plurality of independent trench recesses for forming the buried plate and the collar. SOLUTION: Etching for a trench is made within a surface of a semiconductor substrate 10 and a dielectric material layer is formed on a side wall 12 of the trench. The dielectric material layer is partially eliminated to expose a lower base region of the upper part of the trench side wall 12. After that an oxide layer is made to grow on the upper part of the side wall 12. The dielectric layer is eliminated from a remaining part of the side wall 12 and a buried plate 17 is formed by doping. The dielectric layer includes the upper part of the collar and a node, (i,e, the trench wall at a portion of the buried plate 17) and is provided for the trench wall. An inner electrode 19 is formed at the inner part of the trench.

    EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES
    16.
    发明申请
    EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES 审中-公开
    嵌入式垂直DRAM电池和双功能逻辑门

    公开(公告)号：WO0245130A3

    公开(公告)日：2004-01-08

    申请号：PCT/US0144625

    申请日：2001-11-28

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

    IPC: H01L27/10 ,  H01L21/8242

    CPC classification number: H01L27/10894 ,  H01L27/10864 ,  H01L27/10885 ,  H01L27/10891

    Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.

    Abstract translation: 一种用于生产非常高密度的嵌入式DRAM /非常高性能的逻辑结构的方法，包括在支撑体中制造具有水银源/漏极和栅极导体双功函数MOSFET的垂直MOSFET DRAM单元，包括：在硅衬底中形成法兰电容器， 栅极氧化物层，多晶硅层和沉积在其上的顶部侧面氮化物层; 在阵列和支撑区域上施加图案化掩模并在氮化物层，多晶硅层和浅沟槽隔离区域中形成凹陷; 在氮化物层，多晶硅层和浅沟槽隔离区域的凹槽中形成硅化物和氧化物盖; 施加阻挡掩模以保护支撑物，同时从阵列剥离氮化物层并将暴露的多晶硅层蚀刻到栅极氧化物层的顶部; 从支撑区域剥离氮化物层并在阵列和支撑区域上沉积多晶硅层; 应用掩模来图案化并在阵列中形成位线扩散螺柱着陆焊盘，并在支撑晶体管上形成栅极导体; 打击着陆板和门导体的顶部; 施加层间氧化层，然后在层间氧化层中开通通孔，以建立导电布线通道。

    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE INCLUDING DEEP TRENCH COLLAR
    18.
    发明专利
    METHOD FOR FORMING SEMICONDUCTOR STRUCTURE INCLUDING DEEP TRENCH COLLAR 审中-公开

    公开(公告)号：JP2002026148A

    公开(公告)日：2002-01-25

    申请号：JP2001189096

    申请日：2001-06-22

    Applicant: IBM

    Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE ,  SUDO AKIRA

    IPC: H01L27/108 ,  H01L21/8242

    Abstract: PROBLEM TO BE SOLVED: To provide a new deep trench(DT) collar process which reduces disturbance of strap diffusion to an array metal oxide semiconductor field effect transistor(MOSFET) of a semiconductor device. SOLUTION: By this method, an oxidation barrier layer is formed on a sidewall of the DT provided in the semiconductor substrate, a photoresist layer of specific depth is provided in the trench to remove the oxidation barrier layer to specific depth and expose the trench sidewall, and the remaining photoresist is removed. A layer of a silicon material is stuck on the exposed trench sidewall, and a dielectric layer is formed on the silicon material layer to form a collar. The remaining oxidation barrier layer is removed from the trench and polysilicon which forms a storage node is charged. Consequently, the distance between a MOSFET gate and a DT storage capacitor is maximized, and the effective edge bias of the DT at its peak is reducible without spoiling the storage capacity.

    STRUCTURE AND PROCESS FOR 6F2 TRENCH CAPACITOR DRAM CELL HAVING VERTICAL MOSFET AND 3F BIT LINE PITCH
    19.
    发明专利
    STRUCTURE AND PROCESS FOR 6F2 TRENCH CAPACITOR DRAM CELL HAVING VERTICAL MOSFET AND 3F BIT LINE PITCH 审中-公开

    公开(公告)号：JP2002026147A

    公开(公告)日：2002-01-25

    申请号：JP2001189079

    申请日：2001-06-22

    Applicant: IBM

    Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  KAARU JIEI RADENSU ,  GRUENING ULRIKE

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure including a planar semiconductor substrate. SOLUTION: The semiconductor substrate has a deep trench. The deep trench has side walls and one bottom part. A storage capacitor is located at the bottom of the deep trench. On at least one sidewall of the deep trench, a vertical transistor extends downwardly. This transistor has source diffusion extending in the plane of the substrate adjacent to the deep trench. On at least the other sidewall of the deep trench on the opposite side from the vertical transistor, a separation part extends downwardly. A shallow trench separation area extends laterally to the sidewall, where the vertical transistor extends along the surface of the substrate. In the inside of the deep trench, a gate conductor extends. A word line extends onto the deep trench and is connected to the gate conductor. The bit line extends onto the surface of the substrate and has a contact for the source diffusion between shallow trench separation areas.

    TRANSISTOR EQUIPPED WITH EMBEDDED STRAP CONNECTED TO MEMORY DEVICE
    20.
    发明专利
    TRANSISTOR EQUIPPED WITH EMBEDDED STRAP CONNECTED TO MEMORY DEVICE 失效

    公开(公告)号：JP2000353795A

    公开(公告)日：2000-12-19

    申请号：JP2000139018

    申请日：2000-05-11

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： GRUENING ULRIKE ,  RADENS CARL J

    IPC: H01L27/108 ,  H01L21/60 ,  H01L21/8242 ,  H01L29/732

    Abstract: PROBLEM TO BE SOLVED: To obtain a method of manufacturing an LSI which contains a vertical transistor and is lessened in size, provided at a low cost, and enhanced in reliability. SOLUTION: A capacitor 41 composed of a trench 13, an insulating film 14, and a conductor 16 is formed in a substrate 10, and a stepped part is provided at the upper part of an opening 50 bored in the substrate 10, and then the opening 50 is filled with insulator for the formation of an isolation region 50. The upper part of the stepped part is filled with a conductive material to serve as a strap 904, and N-type ions are implanted for the formation of a source region 61 inside the substrate 10. An insulating film 905 is attached, a gate electrode 108 is deposited, a trench 105 is cut by etching, a spacer 103 is attached, then N-type ions are implanted to form a drain region 106 adjacent to the upper gate 108, and the opening 105 is filled up with conductor to serve as a contact. The strap 904 serves as a source electrode which crosses the capacitor 41 at grade and is electrically connected to the contact 105, which serves as a drain electrode through the intermediary of diffusion regions 61 and 106 located inside the substrate 10.

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