公开(公告)号：GB2495826B

公开(公告)日：2013-11-20

申请号：GB201218064

申请日：2012-10-09

Applicant: IBM

Inventor： CHANG JOSEPHINE ,  GUILLORN MICHAEL ,  GLODDE MARTIN

IPC: H01L29/06 ,  H01L29/423 ,  H01L51/00 ,  H01L51/05

Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.

公开(公告)号：GB2487846A

公开(公告)日：2012-08-08

申请号：GB201203107

申请日：2010-11-04

Applicant: IBM

Inventor： CHANG JOSEPHINE ,  GUILLORN MICHAEL ,  JOSEPH ERIC ANDREW

IPC: H01L51/05 ,  H01L29/06 ,  H01L29/775 ,  H01L29/78 ,  H01L51/00

Abstract: A field effect transistor (FET) comprises a drain formed of a first material, a source formed of the first material, a channel formed by a nanostructure coupling the source to the drain, and a gate formed between the source and the drain and surrounding the nanostructure.

公开(公告)号：GB2497490B

公开(公告)日：2014-02-26

申请号：GB201305905

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： CHANG JOSEPHINE ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786

公开(公告)号：GB2497399B

公开(公告)日：2014-02-19

申请号：GB201221060

申请日：2012-11-23

Applicant: IBM

Inventor： ZHANG YING ,  LIU FEI ,  GUILLORN MICHAEL

IPC: B81C1/00

公开(公告)号：GB2497490A

公开(公告)日：2013-06-12

申请号：GB201305905

申请日：2011-10-03

Applicant: IBM ,  JSR CORP

Inventor： CHANG JOSEPHINE ,  CHARNS LESLIE ,  CUMMINGS JASON E ,  GUILLORN MICHAEL ,  HUPKA LUKASZ J ,  KOLI DINESH ,  KONNO TOMOHISA ,  KRISHNAN MAHADEVAIYER ,  LOFARO MICHAEL F ,  NALASKOWSKI JAKUB W ,  NODA MASAHIRO ,  PENIGALAPATI DINESH K ,  YAMANAKA TATSUYA

IPC: H01L21/304 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786

Abstract: A planarization method includes planarizing a semiconductor wafer in a first chemical mechanical polish step to remove overburden and planarize a top layer leaving a thickness of top layer material over underlying layers. The top layer material is planarized in a second chemical mechanical polish step to further remove the top layer and expose underlying layers of a second material and a third material such that a selectivity of the top layer material to the second material to the third material is between about 1:1:1 to about 2:1:1 to provide a planar topography.

公开(公告)号：GB2495826A

公开(公告)日：2013-04-24

申请号：GB201218064

申请日：2012-10-09

Applicant: IBM

Inventor： CHANG JOSEPHINE ,  GUILLORN MICHAEL ,  GLODDE MARTIN

IPC: H01L29/06 ,  H01L29/423 ,  H01L51/00 ,  H01L51/05

Abstract: A structure includes a substrate 10 having a carbon nanotube 14 disposed over a surface; the carbon nanotube 14 is partially disposed within a protective electrically insulating layer 16; the structure further includes a gate stack disposed over the substrate 10; a first portion of a length of the carbon nanotube 14 not covered by the protective electrically insulating layer 16 passes through the gate stack; source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of carbon nanotube 14 not covered by the protective electrically insulating layer 16 are electrically coupled to the source and drain contacts; the gate stack and the source and drain contacts are contained within the protective electrically insulating layer 16 and within an electrically insulating organic planarization layer 18 that is disposed over the protective electrically insulating layer 16. Also disclosed is a method to fabricate said carbon nanotube-based transistor. Wherein the gate stack may comprise a gate electrode 26 and gate insulator 24, where the gate insulator may comprise a high-k material.