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    CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS
    11.
    发明申请
    CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS 审中-公开
    用于沟槽电容器的碳纳米管导体

    公开(公告)号：WO2005069372A8

    公开(公告)日：2005-11-03

    申请号：PCT/US0340295

    申请日：2003-12-18

    Applicant: IBM ,  FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  NESBIT LARRY A

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

    Abstract: A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

    Abstract translation: 沟槽型存储器件包括在衬底（100）中的沟槽，衬有沟槽的碳纳米管束（202）和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成沟槽衬里的开放柱状结构。 该装置通过在基底上提供碳纳米管催化剂结构并在基底中图案化沟槽而形成; 然后将碳纳米管向下生长到沟槽中以将沟槽与碳纳米管束对齐，之后用沟槽导体填充沟槽。

    WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE
    14.
    发明申请
    WIRING STRUCTURE FOR INTEGRATED CIRCUIT WITH REDUCED INTRALEVEL CAPACITANCE 审中-公开
    具有降低入侵电容的集成电路的接线结构

    公开(公告)号：WO2005104212A3

    公开(公告)日：2006-07-20

    申请号：PCT/US2005013601

    申请日：2005-04-21

    Applicant: IBM ,  WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

    Inventor： WISE RICHARD S ,  CHEN BOMY A ,  HAKEY MARK C ,  YAN HONGWEN

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53295 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features (16) in a layer of dielectric material (13), and forming spacers (20) on sidewalls (16s) of the features. Conductors (25) are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps (40) at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers (42, 12) above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors (25) has a bottom in contact with a low-k dielectric layer (12), a top in contact with another low-k dielectric (42), and sides in contact only with the air gaps (40). The air gaps serve to reduce the intralevel capacitance.

    Abstract translation: 形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层（13）中形成多个特征（16），以及在特征的侧壁（16s）上形成间隔物（20）。 然后，导体（25）形成在特征中，通过间隔件与侧壁分离。 然后去除间隔物，在侧壁处形成气隙（40），使得导体通过气隙与侧壁分离。 在导体上方和下方的介电层（42,12）可以是介电常数小于导体之间的电介质的介电常数的低k电介质。 每个导体（25）的横截面具有与低k电介质层（12）接触的底部，与另一低k电介质（42）接触的顶部和仅与空气接触的侧面 间隙（40）。 气隙用于降低电容值。

    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY
    16.
    发明专利
    METHOD FOR FORMING A HORIZONTAL SURFACE SPACER AND DEVICES FORMED THEREBY 未知

    公开(公告)号：MY117065A

    公开(公告)日：2004-04-30

    申请号：MYPI9904306

    申请日：1999-10-06

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN J ,  HORAK DAVID V ,  RABIDOUX PAUL A

    IPC: H01L21/22 ,  H01L21/033 ,  H01L21/308 ,  H01L21/336 ,  H01L21/425 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78

    Abstract: THE PRESENT INVENTION PROVIDES A METHOD FOR FORMING SELF-ALIGNED SPACERS (502) ON THE HORIZONTAL SURFACES WHILE REMOVING SPACER MATERIAL FROM THE VERTICAL SURFACES. THE PREFERRED METHOD USES A RESIST(302) THAT CAN BE MADE INSOLUBLE TO DEVELOPER BY THE USE OF AN IMPLANT. BY CONFORMALLY DEPOSITING THE RESIST OVER A SUBSTRATE (202) HAVING BOTH VERTICAL AND HORIZONTAL SURFACES, IMPLANTING THE RESIST, AND DEVELOPING THE RESIST, THE RESIST IS REMOVED FROM THE VERTICAL SURFACES WHILE REMAINING ON THE HORIZONTAL SURFACES. THUS, A SELF-ALIGNED SPACER IS FORMED ON THE HORIZONTAL SURFACES WHILE THE SPACER MATERIAL IS REMOVED FROM THE VERTICAL SURFACES. THIS HORIZONTAL-SURFACE SPACER CAN THEN BE USED IN FURTHER FABRICATION. THE PREFERRED METHOD CAN BEUSED IN MANY DIFFERENT PROCESSES WHERE THERE IS EXISTS A NEED TO DIFFERENTIALLY PROCESS THE VERTICAL AND HORIZONTAL SURFACES OF A SUBSTRATE.FIG. 1

    DEVICE CONTACT STRUCTURE AND METHOD FOR FABRICATING SAME.
    19.
    发明专利
    DEVICE CONTACT STRUCTURE AND METHOD FOR FABRICATING SAME. 未知

    公开(公告)号：MY121099A

    公开(公告)日：2005-12-30

    申请号：MYPI9904205

    申请日：1999-09-29

    Applicant: IBM

    Inventor： ALLEN ARCHIBALD J ,  FURUKAWA TOSHIHARU ,  O'NEIL EDWARD F ,  HAKEY MARK C ,  VERHELST ROGER A ,  HORAK DAVID V

    IPC: H01L21/336 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/11

    Abstract: THE PRESENT INVENTION OVERCOMES THE DIFFICULTIES FOUND IN THE BACKGROUND ART BY PROVIDING A DIRECT LOW RESISTIVE CONTACT (101, 102) BETWEEN DEVICES ON A SEMICONDUCTOR CHIP WITHOUT EXCESSIVE CURRENT LEAKAGE. CURRENT LEAKAGE IS PREVENTED IN THE PREFERRED DESIGN BY USING SILICON ON INSULATOR (SOI) CONSTRUCTION FOR THE CHIP. BY CONSTRUCTING THE DIRECT CONTACT OVER AN INSULATOR, SUCH AS SILICON DIOXIDE, CURRENT LEAKAGE IS MINIMIZED. THE PREFERRED EMBODIMENT USES SILICIDE (145, 147) TO CONNECT A POLYSILICON GATE (120, 122) TO A DOPED REGION (230, 235, 237, 830, 835, 837) OF THE SUBSTRATE. AN ALTERNATIVE EMBODIMENT OF THE PRESENT INVENTION PROVIDES FOR THE USE OF CONDUCTIVE STUDS (1910, 1920) TO ELECTRICALLY CONNECT DEVICES. AN INCREASED DENSITY OF APPROXIMATELY TWENTY PERCENT MAY BE REALIZED USING THE PRESENT INVENTION.

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