公开(公告)号：EP0794567A3

公开(公告)日：2000-01-12

申请号：EP97102901

申请日：1997-02-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT L ,  SRINIVASAN RADHIKA ,  HALLE SCOTT D ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  MANDELMAN JACK A ,  JASO MARK ANTHONY

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC classification number: H01L27/10861 ,  H01L21/76232 ,  H01L27/10832 ,  H01L28/82 ,  Y10S438/973

Abstract: A simplified method of fabricating a storage node for a deep trench-based DRAM on a semiconductor substrate. The method involves the etching a trench in a surface of the substrate and then forming a layer of dielectric material on a sidewall of the trench the top portion of which is subsequently removed from the sidewall. Next, a layer of oxide is grown on the exposed portion of the sidewall. A portion of this layer of oxide is then removed from the sidewall in order to orient the layer of oxide a predetermined distance from the surface of the substrate. Finally, the trench is filled with a semiconductive material.

公开(公告)号：JP2000315782A

公开(公告)日：2000-11-14

申请号：JP2000123911

申请日：2000-04-25

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： RUPP THOMAS S ,  DOBUZINSKY DAVID M ,  LU ZHIJIAN

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device which has a stable contact resistance and also has an aligned maximum allowable contact region adapted to reduced fundamental dimensions. SOLUTION: A borderless contact 11 of giga-scale fundamental dimensions is spread in a direction perpendicular to word lines 14 (in a direction parallel to bit lines 16). Formation of a borderless contact structure of another square into a rectangular structure causes reduction of a step positional deviation, thus decreasing a contact resistance and keeping its uniformity. A maximum allowable contact region can be obtained even with a positionally shifted arrangement.

公开(公告)号：JPH11274158A

公开(公告)日：1999-10-08

申请号：JP4899

申请日：1999-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： ARNDT KENNETH C ,  CONTI RICHARD A ,  DOBUZINSKY DAVID M ,  ECONOMIKOS LAERTIS ,  GAMBINO JEFFREY P ,  HOH PETER D ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/76804 ,  H01L21/32136 ,  H01L21/76835 ,  H01L21/76885

Abstract: PROBLEM TO BE SOLVED: To check cracks within a final passivation laver 13 of an integrated circuit by reducing the stresses within a peripheral dielectric which are due to acute corner of a circuit pattern.
SOLUTION: Stresses generally induced inside a dielectric is reduced by formings 15 and 17, at lower corner 14" of a circuit pattern 11 before adhering an outer layer (that is, a passivation layer) 13. When patterning it by metallic RIE process, this kind of rounding of the corner is achieved by a two-step metallic etching process, including the first step of creating a vertical sidewall and the second step of tapering the lower part of the vertical sidewall or creating a tapered spacer 15 along the under section of the vertical sidewall. When patterning it by a die machine process, this kind of rounding of the corner is achieved by a two-step trench etching process, including a first step of creating a vertical sidewall and a second step of creating a tapered side wall along the under section of the vertical sidewall.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过减少外围电介质中由于电路图案的急剧拐角引起的应力来检查集成电路的最终钝化层13内的裂纹。 解决方案：在粘附外层（即钝化层）13之前的电路图案11的下角14“处，通过结构15和17减小电介质内部的应力。当通过金属RIE工艺对其进行图案化时， 通过两步金属蚀刻工艺实现角部的圆角化，包括形成垂直侧壁的第一步骤和使垂直侧壁的下部逐渐变细的第二步骤或者沿着垂直侧壁的下部形成锥形间隔件15 垂直侧壁，当通过模具机加工对其进行图案化时，通过两步沟槽蚀刻工艺实现角部圆化，包括形成垂直侧壁的第一步骤和产生锥形侧壁的第二步骤 沿着垂直侧壁的下部。

公开(公告)号：JP2005005706A

公开(公告)日：2005-01-06

申请号：JP2004167959

申请日：2004-06-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BARD KAREN A ,  DOBUZINSKY DAVID M ,  HO HERBERT L ,  KUMAR MAHENDAR ,  PENDLETON DENISE ,  STEIGERWALT MICHAEL D

IPC: H01L21/77 ,  H01L21/334 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/66181 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/1203 ,  H01L29/7841

Abstract: PROBLEM TO BE SOLVED: To enable the number of stored data bits per chip to be increased in an SOI type integrated circuit device including a DRAM array which is composed of DRAM cells equipped with a trench capacitor.
SOLUTION: When manufacturing the integrated circuit device, the DRAM array is formed in a SOI wafer having a uniform BOX layer 20 extending in the DPAM array. Thereby, (1) a collar oxide film forming process can be skipped, (2) a buried plate 105 can be connected to an ion implantation region 160 which extends through a device layer 30 and the BOX 20 and is connected to a conductive plug biased to the ground. On the other hand, a pass transistor is of a planer type NFET which is equipped with a leakage current electric discharge path connected to the ground through a grounded bit line and also equipped with a floating body.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了在包括由配备有沟槽电容器的DRAM单元组成的DRAM阵列的SOI型集成电路器件中使每芯片的存储数据位数增加。 解决方案：当制造集成电路器件时，DRAM阵列形成在具有在DPAM阵列中延伸的均匀BOX层20的SOI晶片中。 因此，可以跳过（1）环形氧化膜形成工艺，（2）掩埋板105可以连接到离子注入区域160，离子注入区域160延伸穿过器件层30和BOX 20并且连接到导电插塞偏置 到地面。 另一方面，传输晶体管是平面型NFET，其配备有通过接地位线连接到地并且还具有浮体的漏电流放电路径。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000183032A

公开(公告)日：2000-06-30

申请号：JP35042099

申请日：1999-12-09

Applicant: SIEMENS AG ,  IBM

Inventor： PERNG DUNG-CHING ,  DOBUZINSKY DAVID M ,  WANG TING HAO ,  ROITHNER KLAUS

IPC: H01L21/302 ,  H01L21/20 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To restrain silicon from being deposited again on the surface of a wafer so as to prevent a black silicon from being formed, by a method wherein a silicon wafer suitable for the manufacture of semiconductor chips is prepared, a first layer is deposited on all the surface of the wafer, a part of the first layer is removed to expose a region which is suitable for a type of semiconductor device, and then the exposed region is subjected to etching. SOLUTION: An oxide layer 16 is formed on the surface of a wafer 10 where devices are formed, a resist layer is formed on the rear of the wafer 10 so as to cover the layer 16 which is formed on the rear and edge of the wafer 10, and the resist layer is selectively etched to the layer 16. Then, when the front of the wafer 10 is subjected to blanket etching to remove the exposed part of the layer 16, the residual part of the layer 16 covers the edge 22 and the rear of the wafer 10, and the front surface of the wafer 10 is exposed. The resist layer is removed. A pad layer 24 is deposited on all the surface of the wafer 10 and the residual part of the layer 16 and kept in contact with the wafer 10, so that an etched silicon is hardly deposited again on the part of the wafer 10 where the layer 16 is left unremoved.

公开(公告)号：JPH11260798A

公开(公告)日：1999-09-24

申请号：JP1536899

申请日：1999-01-25

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  DOBUZINSKY DAVID M ,  MALINOWSKI JOHN C ,  NG HUNG Y ,  WISE RICHARD S ,  YU CHIENFAN

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To provide a method for anisotropic etching of a nitride layer on a substrate. SOLUTION: In this etching process, an etchant gas containing fluorohydrocarbon rich in hydrogen, oxidant and carbon source is used. It is preferable that the fluorohydrocarbon rich is hydrogen be CH3 or CH2 F2 , the carbon source be CO2 or CO, and the oxidant be O2 . It is preferable that the fluorohydrocarbon exsist in a gas of about 7-35 vol.%, the oxidant exsist in a gas of about 1-35 vol.%, and the carbon source exsists in a gas of about 30-92 vol.%.

公开(公告)号：JP2007150317A

公开(公告)日：2007-06-14

申请号：JP2006317746

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOBUZINSKY DAVID M ,  HO HERBERT L ,  MANDELMAN JACK A ,  OTANI YOICHI

IPC: H01L21/8247 ,  H01L21/265 ,  H01L21/76 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/792 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/7926

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which a vertical trench semiconductor-oxide-nitride-oxide-semiconductor (SONOS) memory cell is formed in a semiconductor-on-insulator (SOI) substrate. SOLUTION: A memory cell comprises: a semiconductor-on-insulator substrate including a top semiconductor layer and a bottom semiconductor layer that are separated from each other by a buried insulating layer; and at least one vertical trench SONOS memory cell located in the semiconductor-on-insulator substrate. The at least one vertical trench SONOS memory cell comprises: a source diffusion located beneath the vertical trench; a selection gate channel located on one side of the vertical trench; an outward-diffused/Si-containing bridge located on and in contact with the selection gate channel; and a silicided doped region located adjacent to and in contact with an upper portion of the bridge. The bridge is present in the top semiconductor layer, the buried insulating layer, and the bottom semiconductor layer. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：提供一种半导体存储器件，其中在绝缘体上半导体（SOI）衬底中形成垂直沟槽半导体氧化物 - 氮化物 - 氧化物半导体（SONOS）存储单元。 解决方案：存储单元包括：绝缘体上半导体衬底，包括通过掩埋绝缘层彼此分离的顶部半导体层和底部半导体层; 以及位于绝缘体上半导体衬底中的至少一个垂直沟道SONOS存储器单元。 所述至少一个垂直沟道SONOS存储单元包括：位于垂直沟槽下方的源极扩散; 位于所述垂直沟槽的一侧上的选择栅极沟道; 位于选择栅极通道上并与选择栅极通道接触的向外扩散/含Si桥; 以及位于与桥的上部相邻并与其接触的硅化物掺杂区域。 该桥存在于顶部半导体层，埋入绝缘层和底部半导体层中。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH11186243A

公开(公告)日：1999-07-09

申请号：JP28213898

申请日：1998-10-05

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  CONLEY WILLARD E ,  COTLER-WAGNER TINA J ,  DELLAGUARDIA RONALD A ,  DOBUZINSKY DAVID M ,  PASSOW MICHAEL L ,  WILLE WILLIAM C

IPC: G03F7/40 ,  G03F7/033 ,  G03F7/039 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311

Abstract: PROBLEM TO BE SOLVED: To provide a resist prescription which is capable of reducing blisters that are generated in a reactive ion etching process to increase the deposit of a resin by-product. SOLUTION: Gaseous fluorocarbon etchant is excited by energy large enough to generate a plasma of high density, wherein the ratio of carbon to fluorine of the etchant is at least 0.33. A resist 12 which is least blistered under the above conditions contains resin binder of terpolymer besides a usual optically active component, wherein the resin binder is composed of (a) a first unit which contains groups unstable to acid, (b) a second unit which does not contain reactive groups and hydroxyl groups, and (c) a third unit which is conducive to development by an aqueous developing agent. The resist, layer 12 on a silicon oxide layer 14 is patterned, and plasma of high density is introduced onto the silicon oxide layer 14, and at least an opening 18 is provided to the silicon oxide layer 14 by etching.

公开(公告)号：JPH10214889A

公开(公告)日：1998-08-11

申请号：JP2253198

申请日：1998-01-21

Applicant: SIEMENS AG ,  IBM

Inventor： HO HERBERT ,  HAMMERL ERWIN ,  DOBUZINSKY DAVID M ,  PALM J HERBERT ,  FUGARDI STEPHEN ,  AJMERA ATUL ,  MOSEMAN JAMES F ,  RAMAC SAMUEL C

IPC: H01L21/76 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To contain a trapping center with a lower density than before conversion, by depositing an Si3 N4 covering with a specific thickness in an STI structure by the low-pressure chemical vapor deposition method, performing speedy heat annealing under specific conditions immediately after depositing the covering, and converting Si3 N4 from amorphous to a crystal material. SOLUTION: After a shallow trench is etched, a thin thermal oxide with a thickness of approximately 10nm is grown to eliminate an etching damage. Then, an Si3 N4 covering with a thickness of 5-10nm is deposited on the upper surface of an oxide layer in amorphous state at a temperature of 720-780 deg.C in a shallow trench isolation structure(STI). Then, immediately after the covering is deposited, a high-speed heat annealing is executed nearly for 60 seconds at 1,050-1,150 deg.C in pure nitrogen or ammonium and the Si3 N4 covering is converted from the amorphous state to the crystal material state of a low- temperature-hexagonal (d) Si3 N4 phase.

公开(公告)号：DE69821458D1

公开(公告)日：2004-03-11

申请号：DE69821458

申请日：1998-11-19

Applicant: IBM

Inventor： ARMACOST MICHAEL D ,  CONLEY WILLARD E ,  COTLER-WAGNER TINA J ,  DELLAGUARDIA RONALD A ,  DOBUZINSKY DAVID M ,  PASSOW MICHAEL L ,  WILLE WILLIAM C

IPC: G03F7/40 ,  G03F7/033 ,  G03F7/039 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: A resist formulation minimizes blistering during reactive ion etching processes resulting in an increased amount of polymer by-product deposition. Such processes involve exciting a gaseous fluorocarbon etchant with sufficient energy to form a high-density plasma, and the use of an etchant having a carbon-to-fluorine ratio of at least 0.33. In addition to a conventional photoactive component, resists which minimize blistering under these conditions include a resin binder which is a terpolymer having: (a) units that contain acid-labile groups; (b) units that are free of reactive groups and hydroxyl groups; and (c) units that contribute to aqueous developability of the photoresist. After the photoresist is patterned on the silicon oxide layer and the high-density plasma is formed, the high-density plasma is introduced to the silicon oxide layer to etch at least one opening in the silicon oxide layer. Preferably, the terpolymer is made up of about 70% 4-hydroxystyrene, about 20% styrene, and about 10% t-butylacrylate.