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    13.
    发明专利
    未知

    公开(公告)号：DE2646343A1

    公开(公告)日：1977-06-30

    申请号：DE2646343

    申请日：1976-10-14

    Applicant: IBM

    Inventor： CHAMBERLAIN SAVVAS GEORGIOU ,  HELLER LAWRENCE GRIFFITH

    IPC: H01L31/10 ,  H01L31/113 ,  H04N3/14

    Abstract: A solid-state charge-coupled photoconductor for image scanning including a p-type substrate having a silicon dioxide layer on the surface thereof with the exception of one or more areas in which an n+ diffusion area is located. A polysilicon gate is located over the silicon dioxide layer and a second silicon dioxide layer is located over the polysilicon layer and the n+ diffusion area except for a portion where a first aluminum contact window is provided which extends through the second silicon dioxide layer to the surface of the n+ diffusion area and where a second aluminum contact window extends through the second polysilicon gate to the surface of the polysilicon gate. The photosensitivity of the device is electronically controlled due to the relatively small n+ layer which is reversed biased with respect to the larger gate area.

    14.
    发明专利
    未知

    公开(公告)号：DE2653059A1

    公开(公告)日：1977-06-08

    申请号：DE2653059

    申请日：1976-11-23

    Applicant: IBM

    Inventor： HELLER LAWRENCE GRIFFITH

    IPC: G11C7/02 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  H01L29/66

    Abstract: An input circuit for a charge-transfer-device such as a bucket-brigade or charge-coupled-device incorporating an input terminal connected to an input diode source diffusion of the charge-transfer-device through a capacitor C. The nonlinear depletion capacitance Cd associated with the input circuit is schematically shown connected in parallel with C at a first node. The non-linear capacitance Cd, which is parasitic, is a basic cause of distortion of the input charge packets. The input circuit further includes an active device such as an IGFET connected in parallel with the input terminal to provide a supply of charge carriers. The gate of the active device is connected to a reset signal source.

    15.
    发明专利
    未知

    公开(公告)号：DE2250140A1

    公开(公告)日：1973-05-17

    申请号：DE2250140

    申请日：1972-10-13

    Applicant: IBM

    Inventor： ARNETT PATRICK CLINTON ,  HELLER LAWRENCE GRIFFITH ,  STAPPER CHARLES HENRI

    IPC: G11C27/04 ,  H01L21/339 ,  H01L29/423 ,  H01L29/43 ,  H01L29/762 ,  H01L29/768 ,  G11C11/34

    Abstract: 1383977 Semi-conductor devices INTERNATIONAL BUSINESS MACHINES CORP 18 Oct 1972 [10 Nov 1971] 47952/72 Heading H1K In a semi-conductor device, such as a shift register or delay line, utilizing the drift of an injected group 30 of minority-charge carriers through a depletion region 23À1 induced in a substrate 10À1 beneath an electrode structure 20À1, there is provided a graded-impurityconcentration region 17À1 of the same conductivity type as the substrate 10À1. The region 17À1 is graded in such a way that in the presence of the appropriate operating voltages on the substrate electrode 21À1, electrode structure 20À1, injecting electrode 15À1 and detecting electrode 16À1. The boundary of the depletion region 23À1 extends parallel to the device surface. In the Si shift register illustrated the electrode structure 20À1 comprises a plurality of interconnected A1 strips capacitively coupled to the ion implanted region 17À1 through a SiO2 layer 18À1. For P-type material a negative bias on the substrate electrode 21À1 induces the depletion region 23À1, the presence of the grounded strips 20À1 producing shallow potential wells 25 which are rapidly filled with injected charge-carriers. A subsequently injected charge-carrier group 30 will drift along the depletion region 23À1, but will tend to become progressively loss spatially localized due to space charge spreading. The group 30 is periodically reshaped by the application of a positive clock pulse to the electrode structure 20À1. Such a pulse temporarily deepens the potential walls 25, causing the drifting group 30 to be trapped and hence relocalized. Using this techique charge-carrier groups may be directed around carriers and in opposed directions. In a simplified embodiment constituting a delay line the electrode structure 20À1 is replaced by a single continuous electrode (20), Fig. 1 (not shown), overlying the whole length of the graded region (17À1), there being in this case no localized potential walls to reshape an injected pulse.

    MEMORY ARRAY
    18.
    发明专利
    MEMORY ARRAY 未知

    公开(公告)号：DE3279355D1

    公开(公告)日：1989-02-16

    申请号：DE3279355

    申请日：1982-07-23

    Applicant: IBM

    Inventor： FIFIELD JOHN ATKINSON ,  HELLER LAWRENCE GRIFFITH ,  WALLS LLOYD ANDRE

    IPC: G11C11/404 ,  G11C11/56 ,  G11C27/02 ,  H01L29/78

    Abstract: A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.

    CLOCKED DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC CIRCUIT
    19.
    发明专利
    CLOCKED DIFFERENTIAL CASCODE VOLTAGE SWITCH LOGIC CIRCUIT 未知

    公开(公告)号：DE3471413D1

    公开(公告)日：1988-06-23

    申请号：DE3471413

    申请日：1984-11-14

    Applicant: IBM

    Inventor： GRIFFIN WILLIAM ROBERT ,  HELLER LAWRENCE GRIFFITH

    IPC: H03K19/0175 ,  H03K19/096 ,  H03K19/173

    Abstract: A clocked differential cascode voltage switch (CVS) logic system is provided for a complete logic family which has a first switching circuit (10) that produces a given output signal at a first output node (14) and a second switching circuit (12) that produces a second output signal which is the complement of that of the given output signal at a second output node (18). First and second clocked devices (24, 28) are connected from the first and second output nodes (14, 18), respectively, to a voltage source (VH), the first and second inverters (32, 34) are connected to the first and second output nodes (14, 18), respectively. Additionally, a regenerative circuit (26, 30) may be connected between the first and second output nodes (14, 18) and the voltage source (VH).

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