公开(公告)号：DE602005005302T2

公开(公告)日：2009-03-12

申请号：DE602005005302

申请日：2005-01-13

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  MITCHELL PETER ,  NESBIT LARRY ALAN

IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

公开(公告)号：DE602005005302D1

公开(公告)日：2008-04-24

申请号：DE602005005302

申请日：2005-01-13

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  MITCHELL PETER ,  NESBIT LARRY ALAN

IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

公开(公告)号：AU624467B2

公开(公告)日：1992-06-11

申请号：AU4778890

申请日：1990-01-08

Applicant: IBM

Inventor： DOBUZINSKY DAVID MARK ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV

IPC: C08G77/06 ,  C08G77/48 ,  C08G77/60 ,  C09D183/00 ,  C09D183/16 ,  C23C14/14 ,  C23C14/24 ,  G03F7/075 ,  G03F7/16 ,  H01L21/027 ,  H01L21/30 ,  H01L21/312 ,  C01B33/04 ,  C23C16/24

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.