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    2.
    发明专利
    未知

    公开(公告)号：DE3686453T2

    公开(公告)日：1993-03-18

    申请号：DE3686453

    申请日：1986-05-16

    Applicant: IBM

    Inventor： ABERNATHEY JOHN ROBERT ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  SEDGWICK THOMAS OLIVER ,  STIFFLER SCOTT RICHARD

    IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/205 ,  H01L21/18 ,  H01L21/306

    Abstract: A method of forming a thin silicon layer (12A) upon which semiconductor devices may be constructed. An epitaxial layer (12A, 12B) is grown on a silicon substrate (10), and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer (14) therein. An oxide layer (16A) is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer (100). The silicon substrate (10) is removed using grinding and/or HNA, the upper portions (12B) of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop (14) is removed using a non-selective etch. The remaining portion of the epitaxy (12A) forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

    4.
    发明专利
    未知

    公开(公告)号：DE69636808T2

    公开(公告)日：2007-11-08

    申请号：DE69636808

    申请日：1996-11-08

    Applicant: IBM

    Inventor： GAMBINO JEFFREY PETER ,  JASO MARK ANTHONY ,  NESBIT LARRY ALAN

    IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/321

    Abstract: Forming inter level studs of at least two different materials, in an insulating layer on a semiconductor wafer comprises: (a) forming a layer of insulating material on a semiconductor wafer; (b) planarising the insulating layer; (c) forming a first group of vias through the insulating layer; (d) forming a layer of first conducting material on the insulating layer; (e) forming a second group of vias through the first conducting material layer and insulating layer; (f) forming a layer of a second conductive material filling the first and second group of vias; (g) removing the second conductive layer to expose the first conductive material layer, such that the second conductive material remains only in the first and second via groups; and (h) removing the exposed first conductive material layer. Also claimed is the method as above in which steps (b),(h) and (i) are achieved by chemically-mechanically polishing, (c) and (e) are etched, and dopant is implanted into the wafer through the second group of vias and the wafer is annealed after (e).

    5.
    发明专利
    未知

    公开(公告)号：DE69636808D1

    公开(公告)日：2007-02-15

    申请号：DE69636808

    申请日：1996-11-08

    Applicant: IBM

    Inventor： GAMBINO JEFFREY PETER ,  JASO MARK ANTHONY ,  NESBIT LARRY ALAN

    IPC: H01L21/768 ,  H01L21/28 ,  H01L21/285 ,  H01L21/304 ,  H01L21/321

    Abstract: Forming inter level studs of at least two different materials, in an insulating layer on a semiconductor wafer comprises: (a) forming a layer of insulating material on a semiconductor wafer; (b) planarising the insulating layer; (c) forming a first group of vias through the insulating layer; (d) forming a layer of first conducting material on the insulating layer; (e) forming a second group of vias through the first conducting material layer and insulating layer; (f) forming a layer of a second conductive material filling the first and second group of vias; (g) removing the second conductive layer to expose the first conductive material layer, such that the second conductive material remains only in the first and second via groups; and (h) removing the exposed first conductive material layer. Also claimed is the method as above in which steps (b),(h) and (i) are achieved by chemically-mechanically polishing, (c) and (e) are etched, and dopant is implanted into the wafer through the second group of vias and the wafer is annealed after (e).

    6.
    发明专利
    未知

    公开(公告)号：DE3584757D1

    公开(公告)日：1992-01-09

    申请号：DE3584757

    申请日：1985-09-03

    Applicant: IBM

    Inventor： KINNEY WAYNE IRVING ,  KOBURGER CHARLES WILLIAM ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  WHITE FRANCIS ROGER ,  TROUTMAN RONALD ROY

    IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/82 ,  H01L21/00

    Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells (26, 28) to each other and also of the field isolation doping regions (32, 10) to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks (30) for subsequent formation of the field-doping regions (32, 10); and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers (32, 10) self-aligned to the wells (26, 28) so that, with a subsequent masking step, oxide field isolations (36, 38) are defined over the doped oxide layers (32, 10). A heat cyde is then used to drive the field dopants into the corresponding field-doping regions (40, 42).

    7.
    发明专利
    未知

    公开(公告)号：DE602005005302T2

    公开(公告)日：2009-03-12

    申请号：DE602005005302

    申请日：2005-01-13

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  MITCHELL PETER ,  NESBIT LARRY ALAN

    IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

    Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

    8.
    发明专利
    未知

    公开(公告)号：DE602005005302D1

    公开(公告)日：2008-04-24

    申请号：DE602005005302

    申请日：2005-01-13

    Applicant: IBM

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  MITCHELL PETER ,  NESBIT LARRY ALAN

    IPC: H01L51/30 ,  H01L21/78 ,  H01L27/28

    Abstract: Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

    Threshold voltage tailoring of corner of mosfet device
    9.
    发明专利
    Threshold voltage tailoring of corner of mosfet device 未知

    公开(公告)号：SG68008A1

    公开(公告)日：1999-10-19

    申请号：SG1997004577

    申请日：1997-12-19

    Applicant: IBM

    Inventor： GAMBINO JEFFERY PETER ,  BRONNER GARY BELA ,  MANDELMAN JACK ALLAN ,  NESBIT LARRY ALAN

    IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8232 ,  H01L27/085

    Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

    10.
    发明专利
    未知

    公开(公告)号：DE3686453D1

    公开(公告)日：1992-09-24

    申请号：DE3686453

    申请日：1986-05-16

    Applicant: IBM

    Inventor： ABERNATHEY JOHN ROBERT ,  LASKY JEROME BRETT ,  NESBIT LARRY ALAN ,  SEDGWICK THOMAS OLIVER ,  STIFFLER SCOTT RICHARD

    IPC: H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/316 ,  H01L21/84 ,  H01L27/12 ,  H01L21/205 ,  H01L21/18 ,  H01L21/306

    Abstract: A method of forming a thin silicon layer (12A) upon which semiconductor devices may be constructed. An epitaxial layer (12A, 12B) is grown on a silicon substrate (10), and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer (14) therein. An oxide layer (16A) is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer (100). The silicon substrate (10) is removed using grinding and/or HNA, the upper portions (12B) of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop (14) is removed using a non-selective etch. The remaining portion of the epitaxy (12A) forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

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