公开(公告)号：WO2008128897A2

公开(公告)日：2008-10-30

申请号：PCT/EP2008054306

申请日：2008-04-09

Applicant: IBM ,  IBM UK ,  CANNON ETHAN HARRISON ,  FURUKAWA TOSHIHARU ,  GAUDIELLO JOHN GERARD ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  KOBURGER III CHARLES WILLIAM ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM ROBERT

Inventor： CANNON ETHAN HARRISON ,  FURUKAWA TOSHIHARU ,  GAUDIELLO JOHN GERARD ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  KOBURGER III CHARLES WILLIAM ,  MANDELMAN JACK ALLAN ,  TONTI WILLIAM ROBERT

CPC classification number: H01L21/76264

Abstract: Hybrid substrates characterized by semiconductor islands of different crystal orientations and methods of forming such hybrid substrates. The methods involve using a SIMOX process to form an insulating layer. The insulating layer may divide the islands of at least one of the different crystal orientations into mutually aligned device and body regions. The body regions may be electrically floating relative to the device regions.

Abstract translation: 以不同晶体取向的半导体岛为特征的混合衬底以及形成这种混合衬底的方法。 这些方法涉及使用SIMOX工艺来形成绝缘层。 绝缘层可以将不同晶体取向中的至少一个的岛分成相互对准的器件区和体区。 本体区域可以相对于器件区域电浮动。

公开(公告)号：JP2007129233A

公开(公告)日：2007-05-24

申请号：JP2006299228

申请日：2006-11-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KOBURGER CHARLES W III ,  HORAK DAVID V ,  HOLMES STEVEN JOHN ,  HAKEY MARK C ,  FURUKAWA TOSHIHARU

IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07

CPC classification number: H01L29/40 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/9202 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002

Abstract: PROBLEM TO BE SOLVED: To improve a manufacturing process of a three-dimensional integrated circuit chip or a wafer assembly, and further in detail, to make it possible to process chips in an arrayed state on a wafer before arranging the chips as stack.
SOLUTION: The manufacture of the three-dimensional integrated circuit is disclosed wherein chip density can be made extremely high, and the wafer can be processed while keeping a planar form as a whole.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：为了改进三维集成电路芯片或晶片组件的制造工艺，并且进一步详细地，可以在将芯片布置在晶片之前以晶片的阵列状态处理芯片为 叠加。 解决方案：公开了三维集成电路的制造，其中芯片密度可以非常高，并且可以在保持平面形状作为整体的同时处理晶片。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005170787A

公开(公告)日：2005-06-30

申请号：JP2004357515

申请日：2004-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES W III ,  MITCHELL PETER H ,  NESBIT LARRY A

IPC: B82B3/00 ,  C01B31/02 ,  C30B25/02 ,  C30B29/02 ,  C30B29/60 ,  H01L29/15 ,  H01L29/786 ,  H01L51/30

CPC classification number: H01L51/0512 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162 ,  C01B2202/22 ,  C01B2202/34 ,  C30B25/02 ,  C30B29/02 ,  C30B29/605 ,  H01L51/0048 ,  Y10S977/854

Abstract: PROBLEM TO BE SOLVED: To provide a method for selecting semiconducting carbon nanotubes from a random collection of conducting and semiconducting carbon nanotubes synthesized on a plurality of synthesis sites carried by a substrate and structures formed thereby.
SOLUTION: After an initial growth stage, synthesis at synthesis sites is interrupted and specific synthesis sites bearing conducting carbon nanotubes are altered so as to halt lengthening of the conducting carbon nanotubes. Synthesis sites bearing semiconducting carbon nanotubes are unaffected by the alteration, so that semiconducting carbon nanotubes can be lengthened to a greater length than the conducting carbon nanotubes.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种从由衬底承载的多个合成位点上合成的导电和半导体碳纳米管的随机集合以及由此形成的结构来选择半导体碳纳米管的方法。 解决方案：在初始生长阶段之后，中断合成位点的合成，改变带有导电碳纳米管的特定合成位点，以阻止导电碳纳米管的延长。 具有半导体碳纳米管的合成位点不受改变的影响，使得半导体碳纳米管可以被延长到比导电碳纳米管更长的长度。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2012145582A

公开(公告)日：2012-08-02

申请号：JP2012016866

申请日：2012-01-30

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN JOHN ,  HORAK DAVID V ,  KOBURGER CHARLES WILLIAM III ,  PASTEL LEAH MARIE PFEIFER

IPC: G01P15/06 ,  G01P15/135 ,  G01R15/06 ,  G01R29/12 ,  H01H35/14

CPC classification number: G01P15/0802 ,  B82Y15/00 ,  G01P15/06 ,  G01P15/0891 ,  G01P15/135 ,  H01H1/0094 ,  H01H35/14

Abstract: PROBLEM TO BE SOLVED: To provide passive maximum acceleration and voltage measurement devices which are compact and do not need a power supply.SOLUTION: A device includes an electrically conductive plate 110 on a top surface of a first insulating layer 105; a second insulating layer 130 on a top surface of the conductive plate 110; and conductive nanotubes 180 suspended across an opening 135 in the second insulating layer 130. Because of acceleration perpendicular to the surface of the conductive plate 110, the nanotubes 180 are bent to be in contact with the conductive plate 110 and held by the van der Waals force.

Abstract translation: 要解决的问题：提供紧凑型无需电源的被动最大加速度和电压测量装置。 解决方案：器件包括在第一绝缘层105的顶表面上的导电板110; 在导电板110的顶表面上的第二绝缘层130; 以及悬挂在第二绝缘层130中的开口135上的导电纳米管180.由于垂直于导电板110的表面的加速度，纳米管180弯曲成与导电板110接触并且被范德华力 力。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2007109632A

公开(公告)日：2007-04-26

申请号：JP2006210142

申请日：2006-08-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK C ,  HOLMES STEVEN JOHN ,  HORAK DAVID V ,  KOBURGER CHARLES WILLIAM III ,  PASTEL LEAH MARIE PFEIFER

IPC: H01H1/26 ,  B81B3/00 ,  G01P15/135 ,  G01R19/04 ,  H01H1/02 ,  H01H35/14 ,  H01H36/00

CPC classification number: G01P15/0802 ,  B82Y15/00 ,  G01P15/06 ,  G01P15/0891 ,  G01P15/135 ,  H01H1/0094 ,  H01H35/14

Abstract: PROBLEM TO BE SOLVED: To provide an acceleration value and voltage measuring device, as well as, a manufacturing method of the acceleration value and voltage measuring device.
SOLUTION: This acceleration value and voltage measuring device has a conductive plate on the upper face of a first insulating layer, a second insulating layer which is the second insulating layer on the upper face of the conductive plate and in which the upper face of the plate is exposed to the opening of the second insulating layer, conductive nanotubes that are bridged over the opening, and conductive contacts to the nanotubes.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供加速度值和电压测量装置，以及加速度值和电压测量装置的制造方法。 解决方案：该加速度值和电压测量装置在第一绝缘层的上表面上具有导电板，第二绝缘层是导电板的上表面上的第二绝缘层，其中上表面 暴露于第二绝缘层的开口，桥接在开口上的导电纳米管和与纳米管的导电接触。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JPH11289069A

公开(公告)日：1999-10-19

申请号：JP1527799

申请日：1999-01-25

Applicant: IBM

Inventor： HORAK DAVID VACLAV ,  FURUKAWA TOSHIHARU ,  HOLMES STEVEN JOHN ,  HAKEY MARK CHARLES ,  MA WILLIAM HSIOH-LIEN ,  MANDELMAN JACK ALLAN

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

公开(公告)号：MX172109B

公开(公告)日：1993-12-03

申请号：MX1946190

申请日：1990-02-12

Applicant: IBM

Inventor： HORAK DAVID VACLAV ,  DOBUZINSKY DAVID MARK ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN

IPC: C08G77/06 ,  C08G77/48 ,  C08G77/60 ,  C09D183/00 ,  C09D183/16 ,  C23C14/14 ,  C23C14/24 ,  G03F7/075 ,  G03F7/16 ,  H01L21/027 ,  H01L21/30 ,  H01L21/312 ,  B41M5/40 ,  C08G77/26

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.

公开(公告)号：DE602005027316D1

公开(公告)日：2011-05-19

申请号：DE602005027316

申请日：2005-02-10

Applicant: IBM

Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES WILLIAM ,  MITCHELL PETER ,  NESBIT LARRY ALAN

IPC: H01L51/05 ,  G11C13/02 ,  H01L21/335 ,  H01L21/336 ,  H01L27/28 ,  H01L29/06 ,  H01L29/12 ,  H01L29/772 ,  H01L51/30 ,  H01L51/40

公开(公告)号：BR9000665A

公开(公告)日：1991-01-15

申请号：BR9000665

申请日：1990-02-14

Applicant: IBM

Inventor： DOBUZINSKY DAVID MARK ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV

IPC: C08G77/06 ,  C08G77/48 ,  C08G77/60 ,  C09D183/00 ,  C09D183/16 ,  C23C14/14 ,  C23C14/24 ,  G03F7/075 ,  G03F7/16 ,  H01L21/027 ,  H01L21/30 ,  H01L21/312 ,  B05D5/12 ,  C23C16/00 ,  G03C5/00

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.

公开(公告)号：AU4778890A

公开(公告)日：1990-08-23

申请号：AU4778890

申请日：1990-01-08

Applicant: IBM

Inventor： DOBUZINSKY DAVID MARK ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN ,  HORAK DAVID VACLAV

IPC: C08G77/06 ,  C08G77/48 ,  C08G77/60 ,  C09D183/00 ,  C09D183/16 ,  C23C14/14 ,  C23C14/24 ,  G03F7/075 ,  G03F7/16 ,  H01L21/027 ,  H01L21/30 ,  H01L21/312 ,  C01B33/04 ,  C23C16/24

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.