公开(公告)号：WO03009380A3

公开(公告)日：2003-08-07

申请号：PCT/GB0201370

申请日：2002-03-21

Applicant: IBM ,  IBM UK

Inventor： CONTI RICHARD ,  DEV PRAKASH ,  DOBUZINSKY DAVID MARK ,  EDELSTEIN DANIEL CHARLES ,  LEE GILL ,  LOW KIA-SENG ,  SHAFER PADRAIC ,  SIMPSON ALEXANDER ,  WRSCHKA PETER

IPC: H01L21/28 ,  H01L21/316 ,  H01L23/532 ,  H01L29/51

CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/02274 ,  H01L21/28194 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and method for an insulator layer having carbon-graded layers above a substrate is disclosed, wherein the concentration of carbon increases in each successive carbon-graded layer above the substrate. The insulator comprises a low-k dielectric having a dielectric constant less than 3.3. The carbon-graded layer increases adhesion between the substrate and the insulator and between the insulator and the conductor layer. The structure may also include stabilization interfaces between the carbon-graded layers. More specifically, the carbon-graded layers include a first layer adjacent the substrate having a carbon content between about 5% and 20%, a second layer above the first layer having a carbon content between about 10% and 30%, and a third layer above the second layer having a carbon content between about 20% and 40%.

Abstract translation: 公开了一种用于在衬底上方具有碳渐变层的绝缘体层的结构和方法，其中在衬底上方的每个连续碳渐变层中的碳浓度增加。 绝缘体包括具有小于3.3的介电常数的低k电介质。 碳渐变层增加了衬底和绝缘体之间以及绝缘体和导体层之间的粘附力。 该结构还可以包括碳梯度层之间的稳定界面。 更具体地说，碳缓变层包括与碳含量在约5％和20％之间的衬底相邻的第一层，在第一层之上的含碳量在约10％和30％之间的第二层，以及第三层 在碳含量在约20％和40％之间的第二层之上。

公开(公告)号：JPH076996A

公开(公告)日：1995-01-10

申请号：JP3886194

申请日：1994-03-09

Applicant: IBM

Inventor： NGUYEN SON VAN ,  DOBUZINSKY DAVID MARK

IPC: C04B41/91 ,  C30B29/38 ,  C30B33/00 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

Abstract: PURPOSE: To allow an etching step to match existing semiconductor device manufacturing processes by etching a boron nitride layer, after doping the layer with an element selected from elements in the IVA group of the periodic table. CONSTITUTION: A boron nitride layer is doped with an element selected from group IVA of the periodic table of the elements such as silicon, carbon or germanium. Then, the doped boron nitride layer is etched using an appropriate etchant, such as a wet etchant (a nitride etchant such as thermal phosphate, hydrofluoric acid, buffer hydrofluoric acid at about 165 deg.C). The amount of dopant used is up to about 20% in atomic composition, but is preferably in a range of amount 2 to 10%. The etching speed of the boron nitride layer is controlled by changing the amount of dopant. As a result, the etching step can match existing semiconductor device manufacturing processes.

公开(公告)号：JPH10214886A

公开(公告)日：1998-08-11

申请号：JP874398

申请日：1998-01-20

Applicant: IBM ,  SIEMENS AG ,  TOSHIBA CORP

Inventor： BENEDICT JOHN PRESTON ,  DOBUZINSKY DAVID MARK ,  FLAITZ PHILIP LEE ,  HAMMERL ERWIN N ,  HO HERBERT ,  MOSEMAN JAMES F ,  PALM HERBERT ,  YOSHIDA SEIKO ,  TAKATO HIROSHI

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To form an effective O2 diffusion barrier by forming a conformal layer that is selected from a group consisting of a double layer that is made of oxide and nitride in a separation groove and on a protection layer, depositing a CVD layer consisting of an oxide-filling material on the layer, and releasing the protection layer and the conformal layer. SOLUTION: A conformal layer 20 with a thickness of approximately 5-15mm being selected from a group consisting of an acid nitride, a double layer consisting of oxide and nitride, and a double layer consisting of acid nitride and nitride is formed on a protection layer (a pad nitride layer 14 and a pad oxide layer 12) and a separation groove (thermal oxide liner) 18. Then, an oxide-filling material 22 such as tetraethylortosilicate with a thickness of 450-500nm is deposited by the CVD supported by ozone, and the oxide-filling material 22 is subjected to anneal treatment and high-density treatment. Then, the conformal layer 20 and the pad nitride layer 14 and the pad oxide layer 12 are released. Then, the oxide-filling material 22 is flattened so that it is flush with the surface of a substrate.

公开(公告)号：WO03015132A9

公开(公告)日：2004-02-19

申请号：PCT/EP0208784

申请日：2002-08-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DOBUZINSKY DAVID MARK ,  KHAN BABAR ALI ,  LIU JOYCE C ,  WENSLEY PAUL ,  YU CHIENFAN

IPC: H01L21/3213 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8242

CPC classification number: H01L27/10894 ,  H01L21/32139 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/10873

Abstract: A method of fabricating an integrated circuit chip having a first region of a first layout rule and a second region of a second layout rule. The method includes using a first material to establish a first hard mask pattern in only the first region and using a second material to establish a second hard mask pattern on top of the first hard mask pattern. The second material is additionally used to establish a third hard mask pattern in the second region.

Abstract translation: 一种制造具有第一布局规则的第一区域和第二布局规则的第二区域的集成电路芯片的方法。 该方法包括使用第一材料仅在第一区域中建立第一硬掩模图案，并且使用第二材料在第一硬掩模图案的顶部上建立第二硬掩模图案。 第二材料另外用于在第二区域中建立第三硬掩模图案。

公开(公告)号：JPH1041465A

公开(公告)日：1998-02-13

申请号：JP10727497

申请日：1997-04-24

Applicant: IBM ,  SIEMENS AG

Inventor： DOBUZINSKY DAVID MARK ,  FUGARDI STEPHEN GERARD ,  HAMMERL ERWIN ,  HO HERBERT LEI ,  RAMAC SAMUEL C ,  STRONG ALVIN WAYNE

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To manufacture a high resistance resistor by using materials and a method common the those used for the integrated circuit process. SOLUTION: As a method for manufacturing a resistor element for an integrated circuit semiconductor device, and insulation film 120 formed is silicon nitride and the like is deposited first. Then, a a film 130 containing titanium is deposited on the insulation film 120. The film 130 and the insulation film 120 are heat-treated so as the diffuse titanium in the insulation film 120. As a result, titanium is diffused in the insulation film 120. Thus, a resistor element with relatively high resistance is manufactured. The merit of this method is that it can be easily integrated with the conventional integrated circuit manufacturing technologies.

公开(公告)号：JP2664866B2

公开(公告)日：1997-10-22

申请号：JP3886194

申请日：1994-03-09

Applicant: IBM

Inventor： NGUYEN SON VAN ,  DOBUZINSKY DAVID MARK

IPC: C04B41/91 ,  C30B29/38 ,  C30B33/00 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311

公开(公告)号：DE69618548D1

公开(公告)日：2002-02-21

申请号：DE69618548

申请日：1996-10-24

Applicant: IBM

Inventor： ARMACOST MICHAEL DAVID ,  DOBUZINSKY DAVID MARK ,  GAMBINO JEFFERY PETER ,  JASO MARK ANTHONY

IPC: H01L21/768 ,  H01L21/304 ,  H01L21/321 ,  H01L21/3105

Abstract: A method of forming interlevel studs in an insulating layer on a semiconductor wafer. First, a conformal BPSG layer is formed on a Front End of the Line (FEOL) semiconductor structure. Vias are opened through the BPSG layer to the FEOL structure. A layer of poly is formed (deposited) on the BPSG layer, filling the vias. The poly layer may be insitu doped poly or implanted after it is deposited. The wafer is annealed to diffuse dopant from the poly to form diffusions wherever the poly contacts the substrate. A non-selective slurry of colloidal silica and at least 1% ammonium hydroxide is used to chem-mech polish the poly from the BPSG layer and, simultaneously, planarize the BPSG layer.

公开(公告)号：DE69534699D1

公开(公告)日：2006-01-26

申请号：DE69534699

申请日：1995-09-22

Applicant: IBM

Inventor： DOBUZINSKY DAVID MARK ,  MATSUDA TETSUO ,  VAN NGUYEN SON ,  RYAN JAMES GARDNER

IPC: C23C16/30 ,  C23C16/40 ,  C23C16/505 ,  H01L21/31 ,  H01L21/316

Abstract: Fluorine-doped oxide is formed that is resistant to water absorption by the use of two sources of silicon, one being the fluorine precursor and the other being available to react with excess fluorine from the fluorine precursor, thereby reducing the number of fluorine radicals in the layer; the fluorine precursor containing a glass-forming element that combines with the other glass constituents to carry into the gas a diatomic radical containing one atom of fluorine and one atom of the glass-forming element. In particular, comparison between traces of undoped oxide and fluorosilicate glass clearly shows that the former has a greater SIOH concentration which is a manufacturing yield detractor.

公开(公告)号：MX172109B

公开(公告)日：1993-12-03

申请号：MX1946190

申请日：1990-02-12

Applicant: IBM

Inventor： HORAK DAVID VACLAV ,  DOBUZINSKY DAVID MARK ,  HAKEY MARK CHARLES ,  HOLMES STEVEN JOHN

IPC: C08G77/06 ,  C08G77/48 ,  C08G77/60 ,  C09D183/00 ,  C09D183/16 ,  C23C14/14 ,  C23C14/24 ,  G03F7/075 ,  G03F7/16 ,  H01L21/027 ,  H01L21/30 ,  H01L21/312 ,  B41M5/40 ,  C08G77/26

Abstract: Disclosed is a process for forming a film comprising a polysilane composition on a substrate. The film is formed by vapor deposition directly on a substrate, thus avoiding the cumbersome steps ordinarily encountered in preparing and applying polysilanes by conventional spin application techniques. The film is used in a lithographic process for forming an image on a substrate.

公开(公告)号：DE69737469T2

公开(公告)日：2007-11-29

申请号：DE69737469

申请日：1997-04-24

Applicant: SIEMENS AG ,  IBM

Inventor： DOBUZINSKY DAVID MARK ,  FUGARDI STEPHEN GERARD ,  HAMMERL ERWIN ,  HO HERBERT LEI ,  RAMAC SAMUEL C ,  STRONG ALVIN WAYNE

IPC: H01L21/3205 ,  H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8244

Abstract: According to the preferred embodiment of the present invention, an improved resistor and method of fabrication is provided. The method for fabricating a resistive element into an integrated circuit semiconductor device comprises the steps of: depositing a dielectric film, such as silicon nitride; depositing a titanium film upon the dielectric film; and annealing the titanium and dielectric films. This causes titanium to be diffused into the dielectric film. This creates a resistive element having a relatively high resistivity. The preferred embodiment method has the advantage of being easily integrated into conventional integrated circuit fabrication techniques.