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    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD
    2.
    发明专利
    TRENCH STORAGE DRAM CELL CONTAINING STEP TRAVEL ELEMENT AND ITS FORMATION METHOD 失效

    公开(公告)号：JPH11289069A

    公开(公告)日：1999-10-19

    申请号：JP1527799

    申请日：1999-01-25

    Applicant: IBM

    Inventor： HORAK DAVID VACLAV ,  FURUKAWA TOSHIHARU ,  HOLMES STEVEN JOHN ,  HAKEY MARK CHARLES ,  MA WILLIAM HSIOH-LIEN ,  MANDELMAN JACK ALLAN

    IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

    Wrap-around type gate field effect transistor
    3.
    发明专利
    Wrap-around type gate field effect transistor 有权
    缠绕型门控场效应晶体管

    公开(公告)号：JP2005175485A

    公开(公告)日：2005-06-30

    申请号：JP2004353618

    申请日：2004-12-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES W III ,  MITCHELL PETER H

    IPC: H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

    Abstract: PROBLEM TO BE SOLVED: To provide a gate formation method capable of controlling the gate length of a self-aligned wrap-around type field effect transistor easily, accurately, and securely. SOLUTION: A reference edge in the vertical direction is determined by forming a cavity in an silicon on insulator (SOI) structure having an embedded silicon island 108. In order to securely carry out an etch back, the reference edge is used in two etch back stages. In the first etch back, part of oxide layer corresponding to a first distance is removed and then, a gate conductive material is applied thereon. In the second etch back, part of the gate conductive material corresponding to a second distance is removed. The difference between the first distance and the second distance determines the final gate length of a device. After the oxide layer is peeled off and removed, gate electrodes 904 and 906 in the vertical direction surrounding the embedded silicon island 108 appear at all four sides. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供能够容易，准确且可靠地控制自对置环绕型场效应晶体管的栅极长度的栅极形成方法。 解决方案：通过在具有嵌入硅岛108的绝缘体上硅（SOI）结构中形成空腔来确定垂直方向上的参考边缘。为了可靠地执行回蚀刻，参考边缘用于 两个回蚀阶段。 在第一回蚀刻中，除去对应于第一距离的部分氧化物层，然后在其上施加栅极导电材料。 在第二次回蚀时，去除对应于第二距离的栅极导电材料的一部分。 第一距离和第二距离之间的差值决定了装置的最终栅极长度。 在去除和除去氧化物层之后，围绕嵌入硅岛108的垂直方向的栅电极904和906出现在所有四个侧面。 版权所有（C）2005，JPO＆NCIPI

    Memory structure and memory structure activation method
    5.
    发明专利
    Memory structure and memory structure activation method 审中-公开
    记忆结构和记忆结构激活方法

    公开(公告)号：JP2007158332A

    公开(公告)日：2007-06-21

    申请号：JP2006322502

    申请日：2006-11-29

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： DAVID VACLAV HORAK ,  KOBURGER CHARLES W III ,  HAKEY MARK CHARLES ,  HOLMES STEVEN J ,  FURUKAWA TOSHIHARU

    IPC: H01L27/10

    CPC classification number: G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0512

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure without gate leak current, and an activation method thereof. SOLUTION: The structure includes (a) a substrate, (b) first and second electrode regions 610, 1120 on the substrate, and (c) a third electrode region 1110 arranged between the first electrode region and the second electrode region. When a first write voltage potential is applied between the first electrode and the third electrode region, in response thereto, the third electrode region changes the shape of its own and then, when a predetermined read voltage potential is applied between the first electrode region and the third electrode region, in response thereto, a sense current flows between the first electrode region and the third electrode region. Further, when a second write voltage potential is applied between the second electrode region and the third electrode region, in response thereto, no sense current flows between the first electrode region and the third electrode region. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供没有栅极泄漏电流的存储单元结构及其激活方法。 解决方案：该结构包括（a）基板，（b）基板上的第一和第二电极区域610,1120，以及（c）布置在第一电极区域和第二电极区域之间的第三电极区域1110。 当在第一电极和第三电极区域之间施加第一写入电压电位时，响应于此，第三电极区域改变其本身的形状，然后当在第一电极区域和第二电极区域之间施加预定的读取电压电位时， 响应于此，感测电流在第一电极区域和第三电极区域之间流动。 此外，当在第二电极区域和第三电极区域之间施加第二写入电压电位时，响应于此，第一电极区域和第三电极区域之间没有感测电流流动。 版权所有（C）2007，JPO＆INPIT

    Movement of lens for immersion optical lithography
    6.
    发明专利
    Movement of lens for immersion optical lithography 有权
    镜头透镜光学平移运动

    公开(公告)号：JP2005197690A

    公开(公告)日：2005-07-21

    申请号：JP2004372593

    申请日：2004-12-24

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HAKEY MARK CHARLES ,  HORAK DAVID V ,  KOBURGER CHARLES W III ,  MITCHELL PETER H

    IPC: G03F7/20 ,  H01L21/027

    CPC classification number: G03F7/70341 ,  G03F7/70258

    Abstract: PROBLEM TO BE SOLVED: To provide a device which can minimize ripples and turbulence associated with the energy transfer between the movement of a lens and a liquid environment.
    SOLUTION: An apparatus for immersion optical lithography has a lens capable of relative movement in synchronization with horizontal motion of a semiconductor wafer in a liquid environment. The synchronized movements of the lens apparatus and the semiconductor wafer advantageously reduce turbulence and air bubbles associated with the liquid environment. The relative motions of the lens and the semiconductor wafer are performed almost simultaneously with a scanning process, resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption in the liquid environment.
    COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种能够使与透镜的运动和液体环境之间的能量传递相关联的波纹和湍流最小化的装置。 解决方案：一种用于浸没光学光刻的设备具有能够在液体环境中与半导体晶片的水平运动同步的相对运动的透镜。 透镜装置和半导体晶片的同步运动有利地减少与液体环境相关联的湍流和气泡。 透镜和半导体晶片的相对运动几乎与扫描过程同时执行，从而在液体环境中产生最小的气泡，湍流和破坏的最佳图像分辨率。 版权所有（C）2005，JPO＆NCIPI

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