公开(公告)号：CH613789A5

公开(公告)日：1979-10-15

申请号：CH533077

申请日：1977-04-28

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DABIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE ,  MCDERMOTT THOMAS STEPHEN ,  WISE LARRY EDWARD

IPC: G06F9/312 ,  G06F12/14 ,  G06F13/12 ,  G06F9/06

Abstract: In the data processing system, one section each (32, 33, 34, 35) of a key register is provided for different types of memory access. A selection circuit (20), the data inputs of which are connected to the key register sections and the control inputs of which are connected to memory access selection signal lines (22, 23, 24, 25) of one or more processors, can be used to select an active memory access key in each case, depending on the type of access. An additional section (31) of the key register is provided for cycle-stealing accesses (memory accesses by a peripheral device without formal program interrupt) and connected to a data input of the selection circuit (20) so that an active memory access key can be selected by means of access signals on a selection signal line (21), connected to another control input of the selection circuit, of an input/output channel mechanism, also including I/O cycle stealing accesses.

公开(公告)号：AU2474777A

公开(公告)日：1978-11-09

申请号：AU2474777

申请日：1977-05-02

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  OSBORNE WILLIAM STEESE ,  KAHN SAMUEL

IPC: G06F9/312 ,  G06F11/00 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24 ,  G06F13/06

Abstract: The disclosure describes instruction operated controls for loading or storing address key values into or from one or more address key register sections in a key-register-controlled addressing system. The controls load or store one or all key register sections of an address key register (AKR) in a processor from or to a word in either a main memory or a general purpose register (GPR). Both the load or store controls are operated by the same instruction format, in which one field indicates whether the operation is to be a load or store of the designated AKR section(s). Another field designates one AKR section, or all AKR sections, which are to be loaded or stored. A still further field designates whether the operation is to be from or to main memory or a GPR. The disclosure provides circuits which operate with microcode to perform these operations.

公开(公告)号：DE2756762A1

公开(公告)日：1978-07-06

申请号：DE2756762

申请日：1977-12-20

Applicant: IBM

Inventor： DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN ,  MAYES GARY WAYNE

IPC: G06F9/305 ,  G06F9/34 ,  G06F12/04 ,  G06F9/06 ,  G06F13/06

Abstract: A method of accessing variable-length bit fields in the memory of an electronic data processing system irrespective of the relationship between the boundaries of addressable elements within said memory and the start and end of the bit fields comprising the operations of: setting the initial values of a base register within said system to contain a representation of a base address of an addressable element; setting the initial values of a shift register within said system to contain a representation of the offset in said memory of the beginning of a particular bit field from said base address; combining the contents of said base and offset registers in such a way as to provide a representation of the position in said memory of the first bit of said particular bit field; create a single instruction that contains a representation of the length of said particular bit field. (Machine-translation by Google Translate, not legally binding)

公开(公告)号：DE2718019A1

公开(公告)日：1977-11-10

申请号：DE2718019

申请日：1977-04-22

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  GRAYBIEL LYNN ALLAN ,  HOOD ROBERT ALLEN ,  BOCA RATON FLA ,  KAHN SAMUEL ,  OSBORNE WILLIAM STEESE

IPC: G06F9/312 ,  G06F12/06 ,  G06F12/14 ,  G06F13/12 ,  G06F9/18

Abstract: The equate operand spaces (EOS) system provides control over the addressabilities accessed by means of different address keys in an address key register (AKR) in a processor. Executing instructions, and their source and sink type operands may have different address keys in the AKR and therefore different addressibilities. When enabled, the EOS control forces each source operand fetch to occur within the sink operand addressability specified in the AKR, even though the AKR explicity contains a different addressability for source operands. When the EOS feature is disabled, the source operand addressability contained in the AKR is used when fetching source operands. An EOS field in the AKr stores whether the EOS state is enabled or disabled in the processor.

公开(公告)号：DE2717654A1

公开(公告)日：1977-11-10

申请号：DE2717654

申请日：1977-04-21

Applicant: IBM

Inventor： BIRNEY RICHARD EUGENE ,  DAVIS MICHAEL IAN ,  HOOD ROBERT ALLEN ,  MCDERMOTT THOMAS STEPHEN ,  WISE LARRY EDWARD

IPC: G06F12/14 ,  G06F11/00

Abstract: The storage protection control system combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in the main memory, to provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses.