公开(公告)号：JP2004363595A

公开(公告)日：2004-12-24

申请号：JP2004159279

申请日：2004-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BELYANSKY MICHAEL P ,  DIVAKARUNI RAMA ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  SETTLEMYER JR KENNETH T ,  SHAFER PADRAIC C

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L21/76229

Abstract: PROBLEM TO BE SOLVED: To provide a method for filling up a separation trench in a silicon integrated circuit having at least one p-n junction or a phase boundary of different materials before forming a separation structure.
SOLUTION: This method relates to filling of the separation trench and a capacitor trench including a perpendicular field-effect transistor (FET) having aspect ratios up to a maximum of 60 (or p-n junction at an arbitrary front level or the phase boundary of the different materials) obtained through a process. The process comprises a step of coating a spin-on material based on silazane with low molecular weight, a step of performing prebake of the coated material at temperature less than about 450°C within oxygen atmosphere, a step of converting the stress of the material by heating within H
2 O atmosphere at intermediate temperature in the range from 450°C-800°C, a step of obtaining a material stable up to a maximum of 1000°C, which has compressive stress which can be adjusted by changing process parameters resulting from heating again within O
2 atmosphere at high temperature, and which has durability sufficiently resisting to CMP having an etching rate comparable to that of oxide dielectrics formed using the high-density plasma (HDP) technique.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2000058779A

公开(公告)日：2000-02-25

申请号：JP21476499

申请日：1999-07-29

Applicant: IBM ,  SIEMENS AG

Inventor： BRONNER GARY B ,  ECONOMIKOS LAERTIS ,  JAMMY RAJARAO ,  PARK BYEONGJU ,  RADENS CARL J ,  SCHREMS MARTIN E

IPC: H01L21/02 ,  H01L21/3215 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a trench capacitor structure suited for use in a semiconductor integrated circuit device and also provide a process sequence used for forming the structure. SOLUTION: A trench structure wherein a trench is demarcated in a semiconductor substrate 100 includes a trench wall, a silicon buried plate 14 doped with conductive species existing in part of the semiconductor substrate around the trench wall, and a silicon structure with texture formed along part of the trench wall. This trench capacitor has improved capacitance by including a capacitor plate constituted of semispherical silicons with texture.

公开(公告)号：JP2005197749A

公开(公告)日：2005-07-21

申请号：JP2005002025

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN ,  DIVAKARUNI RAMA ,  JAMMY RAJARAO

IPC: H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a structure for a perpendicular-type DRAM capable of being integrated into a process flow, using a flat surface device.
SOLUTION: A method of manufacturing an integrated circuit device comprises steps of etching a trench in a substrate; and forming DRAM cells which include a build-up capacitor 24 at a lower edge and a perpendicular-type MOSFET having a gate conductor 30 covering the build-up capacitor 24 and a boron doped channel. The method further comprises a step of forming a trench adjacent to the DRAM cells and a silicon acid nitriding isolation liner at either side of the DRAM cells. Next, an isolation region is formed in the trench at either side of the DRAM cells. Thereafter, the DRAM cells, including a boron-containing channel region are exposed to a high temperature caused by heat treatment to form a supporting device and so on. A nitride containing isolation liner reduces the isolation of boron in a channel region as compared with an oxide-containing isolation liner essentially without nitrogen.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够使用平面装置集成到工艺流程中的垂直型DRAM的结构。 解决方案：一种制造集成电路器件的方法包括以下步骤：蚀刻衬底中的沟槽; 并且在下边缘处形成包括积聚电容器24的DRAM单元和具有覆盖积层电容器24的栅极导体30和掺杂硼的沟道的垂直型MOSFET。 该方法还包括在DRAM单元的任一侧形成与DRAM单元相邻的沟槽和硅酸氮化隔离衬垫的步骤。 接下来，在DRAM单元的任一侧的沟槽中形成隔离区。 此后，包括含硼沟道区的DRAM单元暴露于由热处理引起的高温以形成支撑装置等。 与基本上不含氮的含氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中硼的分离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000091525A

公开(公告)日：2000-03-31

申请号：JP25944099

申请日：1999-09-13

Applicant: IBM

Inventor： JAMMY RAJARAO ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor memory structure, especially a deep trench semiconductor memory device for which a temperature sensitive high dielectric constant material is taken inside the storage node of a capacitor. SOLUTION: In this manufacturing method, after shallow trench separation at high temperature and processing a gate conductor, a deep trench storage capacitor is manufactured. With the manufacturing method, a temperature sensitive high dielectric constant material can be taken into a capacitor structure without causing decomposition of the material. Furthermore, the manufacturing method limits the spread of a buried strap outward diffused part 44, and thus the electric characteristics of an array MOSFET are improved.

公开(公告)号：WO2006076087A2

公开(公告)日：2006-07-20

申请号：PCT/US2005043555

申请日：2005-12-02

Applicant: IBM ,  CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L29/94

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

Abstract translation: 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）的高温下退火HfSiN /高k电介质/界面层之后，界面层的减少，因此栅叠层产生非常小的等效氧化物厚度 （12经典），使用TaSiN无法实现。

公开(公告)号：JP2004193614A

公开(公告)日：2004-07-08

申请号：JP2003409522

申请日：2003-12-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL PATRICK ,  DENNARD ROBERT H ,  DIVAKARUNI RAMA ,  FURMAN BRUCE KENNETH ,  JAMMY RAJARAO ,  NARAYAN CHANDRASEKHAR ,  PURUSHOTHAMAN SAMPATH ,  SHEPARD JR JOSEPH F ,  TOPOL ANNA WANDA

IPC: H01L23/12 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H01L29/40 ,  H05K1/16 ,  H05K3/46

CPC classification number: H05K1/162 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30105 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/09809

Abstract: PROBLEM TO BE SOLVED: To provide a structure for an integrated carrier equipped with high frequency and high speed passive components for computing. SOLUTION: A carrier 200 for a semiconductor component 102 is provided, which has passive components 3010 integrated in its substrate. The passive components 3010 include decoupling components, such as capacitors and resistors. A set of connections 210 is integrated in a close electrical proximity to the supported components. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2004088098A

公开(公告)日：2004-03-18

申请号：JP2003287154

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHUDZIK MICHAEL P ,  BEINTNER JOCHEN ,  RAMACHANDORA DEIVAKARUNI ,  JAMMY RAJARAO

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10867 ,  H01L27/10841 ,  H01L29/66181

Abstract: PROBLEM TO BE SOLVED: To provide a method to form a three-dimensional electrical structure which brings two circuit elements separated in the horizontal and vertical directions into contact, regarding the formation of structures including a DRAM cell comprising a vertical transistor.
SOLUTION: A temporary insulator layer is deposited, and a vertical spacer is formed on the trench walls above the temporary insulator, then the insulator is removed to expose the substrate walls. Next, dopant is diffused into the substrate walls to form a self-aligned extension of a buried strap, and a final gate insulator is deposited, then the upper portion of a DRAM cell is formed.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002026146A

公开(公告)日：2002-01-25

申请号：JP2001180648

申请日：2001-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMA ,  JAMMY RAJARAO ,  BYOON WAI KIMU ,  MANDELMAN JACK A ,  SUDO AKIRA ,  TOBBEN DIRK

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for a trench-type capacitor improved in its charge holding capability. SOLUTION: The memory device includes a trench 23 which is formed on a substrate and has an upper part. A collar oxide film 21 is arranged at the upper part of the trench. A collar oxide film includes a pedestal 25. A conductor is charged in the trench. The pedestal reduces a leak of charges in the conductor. The method for forming the memory device, having the collar oxide film having the pedestal collar, is also disclosed.

公开(公告)号：JP2001358229A

公开(公告)日：2001-12-26

申请号：JP2001134513

申请日：2001-05-01

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： YUN YUU WAN ,  JAMMY RAJARAO ,  KIMBALL LEE J ,  KOTECKI DAVID E ,  LIAN JENNY ,  CHENTEIN RIN ,  MILLER JOHN A ,  NAGEL NICHOLAS ,  SHEN HUA ,  WILDMAN HORATIO S

IPC: H01L27/108 ,  H01L21/02 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a recessed electrode structure which interrupts the crystal grain boundary of an electrode and blocks the diffusion from the side wall. SOLUTION: The capacitor structure comprises an upper platinum electrode, a lower electrode and an insulator on the side wall of the electrode, and the lower electrode has a first recessed portion deposited to the insulator on its side wall and a second insulator portion deposited thereto.

公开(公告)号：DE60122872T2

公开(公告)日：2007-04-19

申请号：DE60122872

申请日：2001-05-02

Applicant: QIMONDA AG ,  IBM

Inventor： WANG YUN-YU ,  JAMMY RAJARAO ,  KIMBALL J ,  KOTECKI E ,  LIAN JENNY ,  LIN CHENTING ,  MILLER A ,  NAGEL NICOLAS ,  SHEN HUA ,  WILDMAN S

IPC: H01L21/02 ,  H01L27/108 ,  H01L21/8242

Abstract: A capacitor structure that comprises a top platinum electrode and a bottom electrode having insulator on the sidewalls of the electrodes, and wherein the bottom electrode is from depositing a first electrode portion being recessed with respect to the insulator on the sidewalls thereof and depositing a second insulator portion is provided.