公开(公告)号：EP1766691A4

公开(公告)日：2011-06-29

申请号：EP05732384

申请日：2005-03-30

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L31/113 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/119

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

公开(公告)号：EP1949447A4

公开(公告)日：2009-11-11

申请号：EP06825854

申请日：2006-10-12

Applicant: IBM

Inventor： CARTER EDUARD A ,  COPEL MATTHEW W ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  LINDER BARRY P ,  NARAYANAN VIJAY

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

公开(公告)号：EP1825521A4

公开(公告)日：2008-10-01

申请号：EP05820881

申请日：2005-11-01

Applicant: IBM

Inventor： BOJARCZUK NESTOR A JR ,  CABRAL CYRIL JR ,  CARTIER EDUARD A ,  FRANK MARTIN M ,  GOUSEV EVGENI P ,  GUHA SUPRATIK ,  JAMISON PAUL C ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC classification number: H01L29/513 ,  H01L21/28194 ,  H01L21/2822 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor structure is provided that includes a V t stabilization layer between a gate dielectric and a gate electrode. The V t stabilization layer is capable of stabilizing the structure's threshold voltage and flatband voltage to a targeted value and comprises a nitrided metal oxide, or a nitrogen-free metal oxide, with the provision that when the V t stabilization layer comprises a nitrogen-free metal oxide, at least one of the semiconductor substrate or the gate dielectric includes nitrogen. The present invention also provides a method of fabricating such a structure.

公开(公告)号：EP1974372A4

公开(公告)日：2009-12-09

申请号：EP07716303

申请日：2007-01-03

Applicant: IBM

Inventor： CHUDZIK MICHAEL P ,  DORIS BRUCE B ,  GUHA SUPRATIK ,  JAMMY RAJARAO ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WANG YUN Y ,  KWONG HON WONG KEITH

IPC: H01L21/336 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/517 ,  H01L21/28088 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP1846947A4

公开(公告)日：2009-04-15

申请号：EP05852630

申请日：2005-12-02

Applicant: IBM

Inventor： VEREECKEN PHILIPPE M ,  BASKER VEERARAGHAVAN ,  CABRAL CYRIL JR ,  COOPER EMANUEL I ,  DELIGIANNI HARIKLIA ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  PARUCHURI VAMSI KRISHNA ,  SAENGER KATHERINE L ,  SHAO XIAOYAN

IPC: H01L21/302 ,  H01L29/745

CPC classification number: H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

Abstract: A method for electroplating a gate metal (9) or other conducting or semiconducting material on a gate dielectric (2) is provided. The method involves selecting a substrate (3, 4), dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be generated at an interface between the dielectric layer and the electrolyte solution or melt.

公开(公告)号：WO02099866A3

公开(公告)日：2003-08-28

申请号：PCT/EP0206916

申请日：2002-06-04

Applicant: IBM ,  COMPANIE IBM FRANCE

Inventor： BALLANTINE ARNE W ,  FALTERMEIER JONATHAN E ,  FLAITZ PHILIP L ,  GILBERT JEFFREY D ,  GLUSCHENKOV OLEG ,  HEENAN CAROL J ,  JAMMY RAJARAO

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/321 ,  H01L21/334 ,  H01L21/8234 ,  H01L29/51

CPC classification number: H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/32105 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66181

Abstract: Disclosed is a method to convert a stable silicon nitride film (101)covering a silicon substrate (100) into a stable silicon oxide film (102) with a low content of residual nitrogen in the resulting silicon oxide film. This is achieved by performing the steps of (i)providing a low pressure environment for the silicon nitride fim of between about l.33 X10 Pa(100 Torr) to about 13.3 Pa (0.1 Torr);(ii)introducing hydrogen and oxygen into said low pressure environment; and iii maintaining said low pressure environment at a temperature of about 600°C to about 1200 C° for a predetermined amount of time. This is an unexpectedand unique property of the in situ steam generation process since both silicon nitride and silicon oxide materials are chemically very stable compounds. Application of the claimed method to the art of microelectronic device fabrication, such as fabrication of on-chip dielectric capacitors and metal insulator semiconductor field effect transistors, is also disclosed.

Abstract translation: 公开了一种将覆盖硅衬底（100）的稳定氮化硅膜（101）转换成所得氧化硅膜中残留氮含量低的稳定氧化硅膜（102）的方法。 这通过以下步骤来实现：（i）为约13.3×10 4 Pa（100托）至约13.3Pa（0.1托）的氮化硅膜提供低压环境;（ii）引入氢 和氧气进入所述低压环境; 以及iii将所述低压环境保持在约600℃至约1200℃的温度下一段预定的时间。 这是原位蒸汽产生过程的意想不到的独特性质，因为氮化硅和氧化硅材料都是化学上非常稳定的化合物。 还公开了所要求保护的方法应用于微电子器件制造领域，例如制造片上电介质电容器和金属绝缘体半导体场效应晶体管。

公开(公告)号：JP2002026143A

公开(公告)日：2002-01-25

申请号：JP2001127022

申请日：2001-04-25

Applicant: IBM

Inventor： GRUENING ULRIKE ,  JAMMY RAJARAO ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To make the thickness of an oxide layer uniform by reducing crystal direction dependency as to a method for forming an oxide layer on the sidewall of a trench formed in a substrate. SOLUTION: This method has a stage, where the trench 200 is formed in the substrate 24, a stage where a nitride interface layer 1250 covering at least part of the sidewall 32 of the trench 200 is formed, a stage where an amorphous layer covering the nitride interface layer 1250 is formed, and a stage where an oxide layer 160 is formed by oxidizing the amorphous layer. Here, a separate collar 130 is arranged, by covering a separate collar nitride interface barrier layer 125 provided between a separate collar oxide layer and the trench sidewall 32, and a vertical gate oxide film 160 is arranged, covering the gate nitride interface layer 1250 provided between the gate oxide layer and trench sidewall 32.

公开(公告)号：EP1872407A4

公开(公告)日：2011-09-14

申请号：EP06750529

申请日：2006-04-18

Applicant: IBM

Inventor： CARTIER EDUARD A ,  COPEL MATTHEW W ,  DORIS BRUCE B ,  JAMMY RAJARAO ,  KIM YOUNG-HEE ,  LINDER BARRY P ,  NARAYANAN VIJAY ,  PARUCHURI VAMSI K ,  WONG KEITH KWONG HON

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823842

公开(公告)号：EP1836732A4

公开(公告)日：2009-07-01

申请号：EP05826298

申请日：2005-12-02

Applicant: IBM

Inventor： CALLEGARI ALESSANDRO C ,  FRANK MARTIN M ,  JAMMY RAJARAO ,  LACEY DIANNE L ,  MCFEELY FENTON R ,  ZAFAR SUFI

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

Abstract: A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000°C), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

公开(公告)号：EP1687457A4

公开(公告)日：2009-06-17

申请号：EP04812387

申请日：2004-11-29

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  DETAVERNIER CHRISTOPHER ,  JAMMY RAJARAO ,  SAENGER KATHERINE L

IPC: H01L21/8238 ,  C23C14/06 ,  C23C16/32 ,  H01L27/108 ,  H01L29/49

CPC classification number: H01L29/4966 ,  H01L21/823842

Abstract: A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.