公开(公告)号：CA2065989C

公开(公告)日：1998-03-31

申请号：CA2065989

申请日：1992-04-14

Applicant: IBM

Inventor： KEENER DON STEVEN ,  VOORHEES RICHARD W ,  MOORE GREGORY JAMES

IPC: G06F13/38 ,  G06F13/28 ,  G06F12/00 ,  G06F13/14

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer system has a high speed local processor data bus, at least one logical processor device coupled directly to the local processor bus and capable of signalling through the local processor bus an occurrence of the transfer of blocks of data, and a storage controller coupled directly to the local processor bus for regulating communications between the processor device and storage memory devices. The storage controller has a FIFO memory for transitory storage of blocks of data being exchanged with the local processor bus and is capable of signalling through the local processor bus the state of the FIFO memory. The processor device and storage controller cooperate for exchange of blocks of data between the local processor bus and FIFO memory when the FIFO memory has available one of data to be transferred and space for reception of data and for emptying of the FIFO memory through the local processor bus as necessary.

公开(公告)号：SG44448A1

公开(公告)日：1997-12-19

申请号：SG1996000492

申请日：1990-06-11

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

IPC: G06F12/06 ,  G06F13/14

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.

公开(公告)号：CA2099025C

公开(公告)日：1996-12-03

申请号：CA2099025

申请日：1993-06-23

Applicant: IBM

Inventor： CHIN ARTHUR LIN ,  ELEAZAR-GARCIA SERAFIN JOSE JR ,  LEE TIMOTHY VINCENT ,  KEENER DON STEVEN ,  MOORE GREGORY JAMES ,  STINE ERIC SPEESTRA

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/38

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

公开(公告)号：CA2065991C

公开(公告)日：1996-01-02

申请号：CA2065991

申请日：1992-04-14

Applicant: IBM

Inventor： KEENER DON STEVEN ,  MOORE GREGORY JAMES

IPC: G06F12/02 ,  G06F13/12 ,  G06F13/28 ,  G06F13/36 ,  G06F13/14

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a small computer systems interface (SCSI) controller coupled directly to the local processor bus for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. The personal computer has a high speed local processor data bus and a storage controller coupled directly to said local processor bus for regulating communications between a processor and storage memory devices. The storage controller has at least one counter for tracking at least one of address and count data for blocks of data being transferred and capable of signalling through the local processor bus the state of the counter, and a bi-stable device interposed between the counter and the local processor bus for enabling delivery to the local processor bus of data representing an initial state of the counter at the beginning of a transfer of blocks of data and for continuing delivery of initial state data throughout a transfer of blocks of data. The counter and bi-stable device cooperate for permitting one of incrementing and decrementing of the counter during transfer of blocks of data while avoiding changes in counter state data delivered to the local processor bus during transfer of blocks of data.

公开(公告)号：DE3687012D1

公开(公告)日：1992-12-03

申请号：DE3687012

申请日：1986-04-18

Applicant: IBM

Inventor： KEENER DON STEVEN

IPC: G11B21/08 ,  G11B5/55 ,  G11B5/596 ,  G11B21/10 ,  G11B21/00

Abstract: Technique for dynamically maintaining alignment of servo controls (12) in a disk (D1, D2) drive system which uses external indicia (Q, R) to position the head assembly (8) between tracks containing embedded servo signals; the latter used to control track following. Plural pairs of phase staggered track reference signals are derived from the external indicia (Q, R) , and during system initialization an optimal pair is selected for controlling head (8) positioning. The system is initialized both at power up time and after detection of certain errors. The selection is made by using each pair separately to direct positioning of the head assembly (8) over a predetermined range of sampling positions at each of which centering offsets relative to the embedded servo signals are measured and recorded in association with the respective pair. Based on an evaluation of these offsets, the system microprocessor (16) selects a reference signal pair having the least average offset to control subsequent head (8) positioning operations. The system is then readied for "normal" read/write operation.

公开(公告)号：PE7291A1

公开(公告)日：1991-03-05

申请号：PE17091390

申请日：1990-06-18

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  OSBORN NEAL ALLEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  NEWSOM THOMAS HAROLD

IPC: G06F12/06 ,  G06F13/14

Abstract: CARACTERIZADO POR PROPORCIONAR UNA CONFIGURACION DE COLECTOR QUE INTERCONECTA UNA PLURALIDAD DE DIRECCIONES ASIGNABLES A INTERFASES DE SISTEMA DE COMPUTADORAS PEQUENAS. UN SEGUNDO COLECTOR AGREGA UN MINIMO DE REQUERIMIENTO DE ENCABLADO, PERO PROPORCIONA LA HABILIDAD PARA CONFIGURAR CADA UNA DE LAS NUEVAS INTERFASES DE SISTEMA DE LA COMPUTADORA PEQUENA CON UNA DIRECCION

公开(公告)号：SG42891A1

公开(公告)日：1997-10-17

申请号：SG1996000456

申请日：1993-05-04

Applicant: IBM

Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  SCHEIERN KEVIN LEE ,  VOORHEES RICHARD W ,  WACHTEL EDWARD IRVING

IPC: G06F13/40 ,  G06F13/36

Abstract: Arrangements are disclosed for physically partitioning a bus having a well defined architecture as a physical entity, wherein the partitioning is logically transparent to a computer and devices which communicate through the bus and serves to avoid problems potentially arising because of the scope of actions permitted by the architecture. A typical bus architecture to which present arrangements have relevance is that associated with SCSI (Small Computer System Interface) buses. The potential problems allowed to occur architecturally involve: (a) exposures of data security/integrity; (b) excessive signal degradation due to use of signal rates which although allowed by the architecture are inappropriate for a particular bus loading environment also allowed by the architecture; (c) restrictions preventing parallel transfer of data between the computer and multiple storage devices; (d) restrictions unduly limiting the number of devices attachable to one logical bus path (one input-output channel of the computer). The disclosed arrangement partitions the bus into two or more physical entities which to the computer appears as one logical entity.

公开(公告)号：SG42889A1

公开(公告)日：1997-10-17

申请号：SG1996000446

申请日：1993-06-17

Applicant: IBM

Inventor： CHIN ARTHUR LIN ,  ELEAZAR-GARCIA SERAFIN J JR ,  LEE TIMOTHY VINCENT ,  KEENER DON STEVEN ,  MOORE GREGORY JAMES ,  STINE ERIC SPEESTRA

IPC: G06F13/362 ,  G06F13/36 ,  G06F13/38 ,  G06F13/364

Abstract: This invention relates to personal computers, and more particularly to a personal computer using a FIFO registers for data transfer as illustrated by a bus master device in the form of a small computer systems interface (SCSI) controller for controlling data transfer with storage memory devices such as fixed or removable media electromagnetic storage devices. In the practice of this invention, the efficiency of a system having a plurality of bus master devices is enhanced by providing for a programmable threshold fill condition for a FIFO register before arbitration for bus control occurs. Thus the invention provides an approach to maximizing the efficiency of data transfer where FIFO registers are used.

公开(公告)号：DE69026018D1

公开(公告)日：1996-04-25

申请号：DE69026018

申请日：1990-09-11

Applicant: IBM

Inventor： KEENER DON STEVEN ,  MCNEILL ANDREW BOYCE ,  WACHTEL EDWARD IRVING

IPC: G06F13/362 ,  G06F13/22 ,  G06F13/24 ,  G06F13/374

Abstract: Apparatus and method for increasing efficiency of command execution from a host processor (11) over an SCSI bus (14). Arbitration, selection and message out functions of SCSI protocol are implemented using a background arbitration state machine (32). Additional protocol functions are implemented in a foreground state machine (26). When the host processor (11) issues a command for access to the SCSI bus (14), the background state machine (32) can be programmed before the foreground machine (26) completes the protocol function for a previous command. Thus, the background state machine (32) is ready to arbitrate for access to the bus (14) at the very next bus free condition.

公开(公告)号：DE69024111D1

公开(公告)日：1996-01-25

申请号：DE69024111

申请日：1990-06-11

Applicant: IBM

Inventor： DIXON JERRY DUANE ,  KEENER DON STEVEN ,  LOCKER HOWARD JEFFREY ,  MARAZAS GERALD ALLAN ,  MCNEILL ANDREW BOYCE ,  NEWSOM THOMAS HAROLD ,  OSBORN NEAL ALLEN

IPC: G06F13/14 ,  G06F12/06

Abstract: Apparatus for assigning addresses to devices connected to an SCSI bus (10). A second configure bus (15) interconnects address assignable devices on the SCSI bus. The assignable devices may be used in a mixed system where some devices have fixed non-assignable addresses. The master device in the SCSI bus transmits configuration commands over the configuration bus and addresses for assignment over the SCSI bus. Acknowledgements are received back from a device which has accepted an address. Once configured with an address, the device propagates subsequent configuration commands to an adjacent device.