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11.发明专利
公开(公告)号：GB2334120B
公开(公告)日：2001-05-02
申请号：GB9909356
申请日：1997-09-30
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , NEAL DANNY MARVIN , KELLEY RICHARD ALLEN
Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
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公开(公告)号：CA2285878A1
公开(公告)日：2000-05-12
申请号：CA2285878
申请日：1999-10-15
Applicant: IBM
Inventor： NEAL DANNY MARVIN , KELLEY RICHARD ALLEN , CLOUSER PAUL LEE
Abstract: An accelerated graphic port connection is adapted for differential signaling. Two signal lines are provided for each graphic port and chipset connection signal and information is encoded as either a polarity or a magnitude of a voltage difference between the two signal lines. An enhanced graphic chip and chipset includes drivers and receivers capable of handling the differential signaling. The resulting accelerated graphic port architecture supports clocking data on both edges as well as source synchronous clocking. The enhanced accelerated graphic port architecture also supports split transactions, deep read pipelining, and the addition of new bus synchronization commands.
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公开(公告)号：DE19782087B4
公开(公告)日：2010-05-20
申请号：DE19782087
申请日：1997-09-30
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , NEAL DANNY MARVIN , KELLEY RICHARD ALLEN
IPC: G06F13/40
Abstract: A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
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公开(公告)号：DE69736872D1
公开(公告)日：2006-12-14
申请号：DE69736872
申请日：1997-03-20
Applicant: IBM
Inventor： GUTHRIE GUY LYNN , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVE MARK
Abstract: A data processing system 10 includes a processor 12, system memory 15 and a number of peripheral devices 401, 403, and one or more bridges 400 which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) 14 and a secondary bus 16. The host bridge 400 provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces is provided.
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Patent Agency Ranking
公开(公告)号：BR0003217A
公开(公告)日：2001-03-13
申请号：BR0003217
申请日：2000-07-31
Applicant: IBM
Inventor： KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVEN MARK
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40 , G06F13/366
Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.
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公开(公告)号：ID21264A
公开(公告)日：1999-05-12
申请号：ID980644
申请日：1998-04-30
Applicant: IBM
Inventor： CLOUSER PAUL L , JOHNS CHARLES RAY , KELLEY RICHARD ALLEN , NEAL DANNY MARVIN , THURBER STEVEN MARK
IPC: G06F13/00 , G06F13/368 , G06F13/38
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公开(公告)号：DE69905689D1
公开(公告)日：2003-04-10
申请号：DE69905689
申请日：1999-11-19
Applicant: IBM
Inventor： NEAL DAN MARVIN , KELLEY RICHARD ALLEN
IPC: G06F13/40
Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.
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公开(公告)号：AT233921T
公开(公告)日：2003-03-15
申请号：AT99309239
申请日：1999-11-19
Applicant: IBM
Inventor： NEAL DAN MARVIN , KELLEY RICHARD ALLEN
IPC: G06F13/40
Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.
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