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    Semiconductor structure and method of manufacturing semiconductor (semiconductor optical sensor)
    11.
    发明专利
    Semiconductor structure and method of manufacturing semiconductor (semiconductor optical sensor) 有权
    半导体结构及制造半导体光电传感器的方法

    公开(公告)号：JP2007142416A

    公开(公告)日：2007-06-07

    申请号：JP2006308607

    申请日：2006-11-15

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KOBURGER CHARLES W III ,  HOLMES STEVEN J ,  FURUKAWA TOSHIHARU ,  DAVID VACLAV HORAK

    IPC: H01L31/02

    CPC classification number: H01L31/101 ,  H01L27/14647 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

    Abstract: PROBLEM TO BE SOLVED: To provide an optical sensor and a method of forming the optical sensor.
    SOLUTION: The optical sensor structure includes (a) a semiconductor substrate, (b) a first, a second, a third, a fourth, a fifth, and a sixth electrodes and (c) a first, a second, and a third semiconductor regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes are at a second depth. The third and sixth electrodes are at a third depth. The first depth is deeper than the second depth, and the second depth is deeper than the third depth. The first semiconductor region, the second semiconductor region, and the third semiconductor region are laid out between the first electrode and the fourth electrode, between the second electrode and the fifth electrode, and between the third electrode and the sixth electrodes, respectively, and are in contact with the first and fourth electrodes, the second and fifth electrodes, and the third and sixth electrodes, respectively. The first semiconductor region, the second semiconductor region, and the third semiconductor region come into contact with each other.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种光学传感器和形成光学传感器的方法。 解决方案：光学传感器结构包括（a）半导体衬底，（b）第一，第二，第三，第四，第五和第六电极和（c）第一，第二和第 第三半导体区域。 第一和第四电极处于第一深度。 第二和第五电极处于第二深度。 第三和第六电极处于第三深度。 第一深度比第二深度深，第二深度比第三深度深。 第一半导体区域，第二半导体区域和第三半导体区域分别布置在第一电极和第四电极之间，第二电极和第五电极之间以及第三电极和第六电极之间，并且分别是 分别与第一和第四电极，第二和第五电极以及第三和第六电极接触。 第一半导体区域，第二半导体区域和第三半导体区域彼此接触。 版权所有（C）2007，JPO＆INPIT

    Wrap-around type gate field effect transistor
    14.
    发明专利
    Wrap-around type gate field effect transistor 有权
    缠绕型门控场效应晶体管

    公开(公告)号：JP2005175485A

    公开(公告)日：2005-06-30

    申请号：JP2004353618

    申请日：2004-12-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： FURUKAWA TOSHIHARU ,  HAKEY MARK CHARLES ,  HORAK DAVID VACLAV ,  KOBURGER CHARLES W III ,  MITCHELL PETER H

    IPC: H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

    CPC classification number: H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

    Abstract: PROBLEM TO BE SOLVED: To provide a gate formation method capable of controlling the gate length of a self-aligned wrap-around type field effect transistor easily, accurately, and securely. SOLUTION: A reference edge in the vertical direction is determined by forming a cavity in an silicon on insulator (SOI) structure having an embedded silicon island 108. In order to securely carry out an etch back, the reference edge is used in two etch back stages. In the first etch back, part of oxide layer corresponding to a first distance is removed and then, a gate conductive material is applied thereon. In the second etch back, part of the gate conductive material corresponding to a second distance is removed. The difference between the first distance and the second distance determines the final gate length of a device. After the oxide layer is peeled off and removed, gate electrodes 904 and 906 in the vertical direction surrounding the embedded silicon island 108 appear at all four sides. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供能够容易，准确且可靠地控制自对置环绕型场效应晶体管的栅极长度的栅极形成方法。 解决方案：通过在具有嵌入硅岛108的绝缘体上硅（SOI）结构中形成空腔来确定垂直方向上的参考边缘。为了可靠地执行回蚀刻，参考边缘用于 两个回蚀阶段。 在第一回蚀刻中，除去对应于第一距离的部分氧化物层，然后在其上施加栅极导电材料。 在第二次回蚀时，去除对应于第二距离的栅极导电材料的一部分。 第一距离和第二距离之间的差值决定了装置的最终栅极长度。 在去除和除去氧化物层之后，围绕嵌入硅岛108的垂直方向的栅电极904和906出现在所有四个侧面。 版权所有（C）2005，JPO＆NCIPI

    PROCESS OF MAKING DUAL WELL CMOS SEMICONDUCTOR STRUCTURE WITH ALIGNED FIELD-DOPINGS USING SINGLE MASKING STEP
    17.
    发明专利
    PROCESS OF MAKING DUAL WELL CMOS SEMICONDUCTOR STRUCTURE WITH ALIGNED FIELD-DOPINGS USING SINGLE MASKING STEP 未知

    公开(公告)号：CA1209280A

    公开(公告)日：1986-08-05

    申请号：CA485177

    申请日：1985-06-25

    Applicant: IBM

    Inventor： KINNEY WAYNE I ,  KOBURGER CHARLES W III ,  LASKY JEROME B ,  NESBIT LARRY A ,  TROUTMAN RONALD R ,  WHITE FRANCIS R

    IPC: H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

    Abstract: PROCESS OF MAKING DUAL WELL CMOS SEMICONDUCTOR STRUCTURE WITH ALIGNED FIELD-DOPINGS USING SINGLE MASKING STEP A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implanation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

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