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公开(公告)号：NZ245347A
公开(公告)日：1995-09-26
申请号：NZ24534792
申请日：1992-12-02
Applicant: IBM
Inventor： AMINI NADER , BOURY BECHARA FOUAD , BRANNON SHERWOOD , HORNE RICHARD LOUIS , LOHMAN TERENCE JOSEPH
Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.
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公开(公告)号：NZ245346A
公开(公告)日：1995-09-26
申请号：NZ24534692
申请日：1992-12-02
Applicant: IBM
Inventor： ALDEREGUIA ALFREDO , AMINI NADER , HORNE RICHARD LOUIS , LOHMAN TERENCE JOSEPH , TRAN CANG NGOC
Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.
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公开(公告)号：DE69421453T2
公开(公告)日：2000-05-18
申请号：DE69421453
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
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公开(公告)号：AT186412T
公开(公告)日：1999-11-15
申请号：AT94303783
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
Abstract: A direct memory access (DMA) support mechanism is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24 connected to system memory 32 by a first system bus 36, and a second system bus 16 connected to the CPU; (ii) a host bridge 20 connecting the second system bus to a peripheral bus 22; (iii) an input/output (I/O) bridge 78 connecting the peripheral bus to a standard I/O bus 92, the standard I/O bus having a plurality of standard I/O devices 90 attached thereto; and (v) arbitration logic 42 which functions in an arbitration mode for arbitrating between the plurality of standard I/O devices competing for access to the standard I/O bus, and in a grant mode wherein a selected standard I/O device is granted access to the standard I/O bus. The DMA support mechanism comprises a direct memory access (DMA) controller 40 for performing DMA cycles on behalf of the selected standard I/O device, and direct memory access (DMA) support logic for enabling the DMA cycles to be performed over the peripheral bus. The DMA support logic includes sideband signals directly connecting the DMA controller with the I/O bridge, the sideband signals including information identifying the bus size of the selected I/O device for which the DMA controller is performing the DMA cycles.
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公开(公告)号：CA2080210C
公开(公告)日：1998-10-27
申请号：CA2080210
申请日：1992-10-08
Applicant: IBM
Inventor： LOHMAN TERENCE JOSEPH , AMINI NADER , BOURY BECHARA FOUAD , BRANNON SHERWOOD , HORNE RICHARD LOUIS
Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.
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Patent Agency Ranking
公开(公告)号：IN181078B
公开(公告)日：1998-04-18
申请号：IN658MA1992
申请日：1992-10-30
Applicant: IBM
Inventor： HORNE RICHARD LOUIS , LOHMAN TERENCE JOSEPH , BRANNON SHERWOOD , BOURY BECHARA FOUAD , NADER AMINI
IPC: G06F13/16
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公开(公告)号：SG44446A1
公开(公告)日：1997-12-19
申请号：SG1996000483
申请日：1992-12-22
Applicant: IBM
Inventor： AMINI NADER , BOURY BECHARA FOUAD , SRANNON SHERWOOD , HORNE RICHARD LOUIS , LOHMAN TERENCE JOSEPH
Abstract: The present invention provides a bus to bus interface unit for computer systems having dual bus architecture, such as a system bus and an I/O bus. The bus interface unit includes an asynchronous bidirectional temporary data storage function for data being transferred between the two buses to and from devices coupled to each of the two buses. Preferably the storage function operates in modes that will accommodate individual transfers of data, data streaming, and data burst transfers, and can accommodate transfers of information from contiguous addresses without initiating a new request for each address.
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公开(公告)号：SG42882A1
公开(公告)日：1997-10-17
申请号：SG1996000412
申请日：1992-12-18
Applicant: IBM
Inventor： AMINI NADER , BOURY BECHARA FOUAD , HORNE RICHARD LOUIS , LOHMAN TERENCE JOSEPH
IPC: G06F13/22 , G06F13/36 , G06F13/28 , G06F13/362 , G06F13/20
Abstract: A computer system is provided comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to a plurality of input/output devices by an input/output bus. The bus interface unit is able to sense when said one of said input/output devices has completed a read or write operation over said input/output bus, and includes a buffer circuit wherein read and write data transferred between the system bus and the input/output bus via the bus interface unit is temporarily stored during the transfer. Arbitration control logic resides in said bus interface unit and interacts with a central arbitration controller which resides on the system bus. The central arbitration controller responds to the arbitration control logic to simultaneously perform (i) arbitration cycles wherein the central arbitration controller arbitrates between the plurality of input/output devices and the central processing unit to determine which of the input/output devices or the central processing unit should be granted control of the input/output bus and (ii) grant cycles wherein the central arbitration controller grants control of the input/output bus and extends control of the system bus to one of the input/output devices or the central processing unit.
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公开(公告)号：DE69423056T2
公开(公告)日：2000-09-14
申请号：DE69423056
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.
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公开(公告)号：DE69423056D1
公开(公告)日：2000-03-30
申请号：DE69423056
申请日：1994-05-25
Applicant: IBM
Inventor： AMINI NADER , BLAND PATRICK MAURICE , BOURY BECHARA FOUAD , HOFMANN RICHARD GERARD , LOHMAN TERENCE JOSEPH
IPC: G06F13/36 , G06F13/362 , G06F13/364 , G06F13/40
Abstract: An arbitration mechanism 42 is provided for use in a computer system 10 which comprises (i) a central processing unit (CPU) 24; (ii) a first system bus 36 which connects the CPU 24 to system memory 32 so that the CPU 24 can read data from, and write data to, the system memory 32; (iii) a second system bus 16 connected to the CPU 24; (iv) a host bridge 20 connecting the second-system bus 16 to a peripheral bus 22, the peripheral bus 22 having at least one peripheral device 18 attached thereto; and (v) an input/output (I/O) bridge 78 connecting the peripheral bus 22 to a standard I/O bus 92, the standard I/O bus 92 having a plurality of standard I/O devices 90 attached thereto. The arbitration mechanism 42 comprises (i) a first level 100 of logic for arbitrating between the plurality of standard I/O devices 90, wherein one standard I/O device 90 is selected from a plurality of the standard I/O devices 90 competing for access to the standard I/O bus 97, and (ii) a second level 102, 104 of logic for arbitrating between the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18, wherein one of the selected standard I/O device 90, the CPU 24 and the at least one peripheral device 18 is selected to access the peripheral bus 22. The arbitration mechanism 42 includes sideband signals which connect the first 100 and second levels 102, 104 of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device 90.
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