公开(公告)号：AU575499B2

公开(公告)日：1988-07-28

申请号：AU6307186

申请日：1986-09-23

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/20 ,  H01L29/04 ,  H01L29/10 ,  H01L29/78

Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：DE3767962D1

公开(公告)日：1991-03-14

申请号：DE3767962

申请日：1987-10-02

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN ,  MACHESNEY BRIAN JOHN ,  MOHLER RICK LAWRENCE ,  MILES GLEN LESTER ,  TING CHUNG-YU ,  WARLEY STEPHEN DAVID

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/482 ,  H01L23/52 ,  H01L29/45 ,  H01L21/285 ,  H01L29/62

公开(公告)号：IN167820B

公开(公告)日：1990-12-22

申请号：IN596MA1986

申请日：1986-07-28

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/00

Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：DE3572422D1

公开(公告)日：1989-09-21

申请号：DE3572422

申请日：1985-05-23

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN ,  NING TAK HUNG ,  TERMAN LEWIS MADISON

IPC: H01L27/108 ,  H01L29/94 ,  H01L27/10 ,  G11C11/24

公开(公告)号：ZA866625B

公开(公告)日：1987-06-24

申请号：ZA866625

申请日：1986-09-01

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01C ,  H01L

Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：BR8604546A

公开(公告)日：1987-05-26

申请号：BR8604546

申请日：1986-09-23

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/76 ,  H01L27/02

Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：AU6307186A

公开(公告)日：1987-04-30

申请号：AU6307186

申请日：1986-09-23

Applicant: IBM

Inventor： LU NICKY CHAU-CHUN

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/108 ,  H01L21/20 ,  H01L29/04 ,  H01L29/10 ,  H01L29/78

Abstract: Dynamic random access memory (DRAM) devices are described wherein individual cells, including an access transistor and a storage capacitor are formed on a single-crystal semiconductor chip, and more particularly a three-dimensional dynamic random access memory (DRAM) device structure is described having a single-crystal access transistor stacked on top of a trench capacitor. A fabrication method for such devices is also described wherein crystallisation seeds are provided by the single-crystal semiconductor area surrounding the cell and/or from the vertical sidewalls of the trench and wherein the access transistor is isolated by insulator. In the structure, a trench is located in a p+ type substrate containing heavily doped N+ polysilicon. A composite film of SiO₂/Si₃N₄/SiO₂ is provided for the capacitor storage insulator. A thin layer of SiO₂ is disposed over the polysilicon. A lightly doped p-type epi silicon layer is located over the substrate and SiO₂ layer. The access transistor for the memory cell is located on top of the trench capacitor. An N+ doped material connects the source region of the transistor to the polysilicon inside the trench. A medium doped p-region on top of the trench surface may be provided in case there is any significant amount of leakage current along the trench surface.

公开(公告)号：DE69027705T2

公开(公告)日：1997-01-23

申请号：DE69027705

申请日：1990-03-29

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE69027705D1

公开(公告)日：1996-08-14

申请号：DE69027705

申请日：1990-03-29

Applicant: IBM

Inventor： DHONG SANG HOO ,  HWANG WEI ,  LU NICKY CHAU-CHUN

IPC: G11C11/407 ,  G11C11/408 ,  H03K5/02

Abstract: An improved wordline boost clock circuit that can be used in high speed DRAM circuits requires only one boost capacitor (42) and discharges the wordlines faster, thus improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the NMOS device which drives the load to negative during the boosting. In a first embodiment of the clock (Fig. 2), the gate of a first device (24) is connected to a first node (26) through a second device (28). A second node (30), connected to a wordline, is discharged through the first (24) and a third (32) device when a third node (36) is high with a fourth node (38) low. After a sufficient discharge of the second node (30), the fourth node (38) is pulled to VDD turning the second device (28) on and a fourth device (40) off. The first (NMOS) transistor (24) has its gate and drain connected together and forms a diode. When a boost capacitor (42) pulls the first node (26) down to negative, the first device (24) stays completely off because of its diode configuration and the second node (30) is pulled to negative through the third device (32). In a second embodiment (Fig. 3), a first device (24) is connected between a boost capacitor and a second node (30). The load is discharged through a third device (32) with a fourth device (40) on but a first (24) and second device (28) off. After a sufficient discharge of the load, a fourth device (40) is turned off but a second device (28) is turned on, making the third device (32) a diode. When a fifth node (74) is pulled to ground, the second node 30 is pulled down to negative with the first device (24) on. In the second embodiment circuit the load discharges through only one NMOS device (32) and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：DE3886632T2

公开(公告)日：1994-06-23

申请号：DE3886632

申请日：1988-08-05

Applicant: IBM

Inventor： DHONG SANG HOO ,  LU NICKY CHAU-CHUN

IPC: G11C11/409 ,  G11C7/06 ,  G11C11/4091