公开(公告)号：BR9402596A

公开(公告)日：1995-06-13

申请号：BR9402596

申请日：1994-06-29

Applicant: IBM

Inventor： GALAND CLAUDE ,  LEBIZAY GERALD ,  MAUDUIT DANIEL ,  MUNIER JEAN-MARIE ,  PAUPORTE ANDRE ,  SAINT-GEORGES ERIC ,  SPAGNOL VICTOR

IPC: H04L29/06 ,  H04L12/56

Abstract: A high performance data packet buffering method and a programmable data communication adapter for high speed packet transmission networks are disclosed. The line adapter includes programmable processing means, for receiving and transmitting data packets of fixed or variable length. This system is characterized in that it comprises means for buffering (132) said data packets, means for identifying said buffering means and said data packets in said buffering means, means for queueing (Figure 15) in storing means (131) said identifying means in a single instruction, means for dequeueing (Figure 16) from said storing (131) means said identifying means in another single instruction , means for releasing said buffering means, Each instruction comprises up to three operations executed in parallel by said processing means : an arithmetical and logical (ALU) operation on said identifying means, a memory operation on said storing means, and a sequence operation.

公开(公告)号：DE3881883D1

公开(公告)日：1993-07-22

申请号：DE3881883

申请日：1988-08-30

Applicant: IBM

Inventor： CUKIER MAURICE ,  MAUDUIT DANIEL ,  ORENGO GERARD

IPC: H03M3/04 ,  H03H17/00 ,  H03H17/06 ,  H04L7/033

Abstract: The digital filter has clocking in and out frequencies F and submultiple f respectively, the frequency f being synchronised with a remote clock. The ratio F to f determines the number of taps and accumulators (38,40,42) which add the products to tap coefficients and incoming signals (S1,S2,S3) loaded during each clock cycle at frequency F by processing circuit (32,34,36). The accumulators are clocked out sequentially at frequency f and multiplexer (44) selects the next accumulator to be loaded. A zero value tap ensures the last product output is always zero allowing synchronisation. A clock cycle frequency F may be added or skipped. Frequency f is adjusted by a phase locked loop. Both F . and f are generally derived in a single oscillator.