公开(公告)号：DE68922715T2

公开(公告)日：1996-01-25

申请号：DE68922715

申请日：1989-12-23

Applicant: IBM

Inventor： MEMIS IRVING ,  ROVENTE FREDERICK M

IPC: C23F1/00 ,  G03F7/11 ,  G03F7/20 ,  H05K3/00 ,  H05K3/06 ,  H05K3/38 ,  B29C70/00 ,  B32B31/00 ,  G03F7/16

公开(公告)号：CA1085984A

公开(公告)日：1980-09-16

申请号：CA267528

申请日：1976-12-09

Applicant: IBM

Inventor： BAKOS PETER ,  MEMIS IRVING ,  RASILE JOHN

IPC: H05K5/00 ,  C09D4/00 ,  H01L21/312 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K5/06 ,  C09D3/74 ,  B05D3/02

Abstract: HERMETIC POLYMERIC TOPSEALANT COATING FOR ELECTRONIC CIRCUITRY A hermetic topsealant for metal electrodes on components and other microelectronic circuitry is formed by polymerizing a mixture of an unsaturated silane monomer, a bifunctional silane adhesion promoter, a polymeric plasticizer and a stabilizer.

公开(公告)号：DE60334230D1

公开(公告)日：2010-10-28

申请号：DE60334230

申请日：2003-09-15

Applicant: IBM

Inventor： MACQUARRIE STEPHEN WESLEY ,  MEMIS IRVING

IPC: H01L21/60 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34

公开(公告)号：AT481734T

公开(公告)日：2010-10-15

申请号：AT03798966

申请日：2003-09-15

Applicant: IBM

Inventor： MACQUARRIE STEPHEN ,  MEMIS IRVING

IPC: H01L21/60 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34

Abstract: In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.

公开(公告)号：DE68922715D1

公开(公告)日：1995-06-22

申请号：DE68922715

申请日：1989-12-23

Applicant: IBM

Inventor： MEMIS IRVING ,  ROVENTE FREDERICK M

IPC: C23F1/00 ,  G03F7/11 ,  G03F7/20 ,  H05K3/00 ,  H05K3/06 ,  H05K3/38 ,  B29C70/00 ,  B32B31/00 ,  G03F7/16

公开(公告)号：AU2003263368A1

公开(公告)日：2004-04-23

申请号：AU2003263368

申请日：2003-09-15

Applicant: IBM

Inventor： MACQUARRIE STEPHEN WESLEY ,  MEMIS IRVING

IPC: H01L21/60 ,  H01L23/13 ,  H01L23/50 ,  H05K1/02 ,  H05K3/34 ,  H01L23/498

Abstract: In an integrated circuit package employing solder bump technology, a metal layer placed on the surface of a substrate below an array of bonding pads is split and displaced from its axis at selected locations to preserve electrical continuity, but to also lower the height of an insulating solder mask layer at those locations.

公开(公告)号：DE69800514D1

公开(公告)日：2001-03-08

申请号：DE69800514

申请日：1998-05-26

Applicant: IBM

Inventor： MEMIS IRVING

IPC: H05K3/46 ,  H01L21/60 ,  H01L23/12 ,  H01L23/538 ,  H05K1/11 ,  H05K3/40 ,  H05K1/00 ,  H01L23/498

Abstract: A circuit board is provided which has contacts on the surface arrayed to engage contact pads on a chip carrier bounded by a grid. A plurality of primary through holes are provided in the circuit board location within the grid in an interstitial array and electrically connected to respective first chip contact pads thereabove. A plurality of secondary through holes are provided which are located outside the grid and electrically connected to respective second chip contact pads.

公开(公告)号：DE69220333D1

公开(公告)日：1997-07-17

申请号：DE69220333

申请日：1992-10-19

Applicant: IBM

Inventor： BONITZ BARRY ALAN ,  ELLERSON JAMES VERNON ,  KAPUR KISHEN NARAIN ,  MCCREARY JACK MARLYN ,  MEMIS IRVING ,  VETTEL GERALD MICHAEL

IPC: H01L23/50 ,  H01L23/04 ,  H05K1/18 ,  H05K3/28 ,  H05K3/34 ,  H05K13/00 ,  H01L21/00

Abstract: An electronic package assembly (10) wherein a low profile package is soldered to an organic (e.g., epoxy resin) substrate (11) (e.g., printed circuit board), the projecting conductive leads (21) of the package and the solder (53) which substantially covers these leads (and respective conductors on the substrate) having been substantially covered with encapsulant material (61) (e.g., polymer resin) to provide reinforcement for the solder-lead connections. The encapsulant material is dispensed about the solder and lead joints following solder reflow and solidification so as to substantially surround the solder and any portions of the leads not covered with solder. The invention has particular useful with thin, small outline package (TSOP) structures which occupy a minimum of height on the substrate surface.

公开(公告)号：CA1134096A

公开(公告)日：1982-10-19

申请号：CA341841

申请日：1979-12-13

Applicant: IBM

Inventor： DARROW RUSSELL E ,  MEMIS IRVING ,  POLIAK RICHARD M

IPC: H01L23/055 ,  H01L23/10 ,  C08G59/58 ,  C08L63/00 ,  H01L23/02

Abstract: The hermetic seal of the backside of a substrate of an integrated circuit module is provided by a composition containing about 51.4 to about 60.6% by weight of an epoxy polymer; about 39 to about 48% by weight of a hardener and flexibilizing portion; and up to about 0.6% by weight of a coloring agent.

公开(公告)号：DE2656139A1

公开(公告)日：1977-06-23

申请号：DE2656139

申请日：1976-12-10

Applicant: IBM

Inventor： BAKOS PETER ,  MEMIS IRVING ,  RASILE JOHN

IPC: H05K5/00 ,  C09D4/00 ,  H01L21/312 ,  H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K5/06

Abstract: A hermetic topsealant for metal electrodes on components and other microelectronic circuitry is formed by polymerizing a mixture of an unsaturated silane monomer, a bifunctional silane adhesion promoter, a polymeric plasticizer and a stabilizer.