中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

16 records (took 0.016 seconds)

    INTEGRATED CIRCUIT ISOLATION STRUCTURE AND METHOD FOR PRODUCING THE ISOLATION STRUCTURE
    11.
    发明专利
    INTEGRATED CIRCUIT ISOLATION STRUCTURE AND METHOD FOR PRODUCING THE ISOLATION STRUCTURE 未知

    公开(公告)号：CA1066815A

    公开(公告)日：1979-11-20

    申请号：CA266780

    申请日：1976-11-29

    Applicant: IBM

    Inventor： ABOAF JOSEPH A ,  BROADIE ROBERT W ,  PLISKIN WILLIAM A

    IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73

    Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to the dense structure which is substantially planar with the surface of the semiconductor wafer. This densified silicon dioxide structure has an etch rate which is substantially the same as thermally grown silicon dioxide.

    METHOD FOR FORMING RECESSED ISOLATED REGIONS
    14.
    发明专利
    METHOD FOR FORMING RECESSED ISOLATED REGIONS 未知

    公开(公告)号：CA1166762A

    公开(公告)日：1984-05-01

    申请号：CA404056

    申请日：1982-05-28

    Applicant: IBM

    Inventor： PLISKIN WILLIAM A ,  RISEMAN JACOB ,  SHEPARD JOSEPH F

    IPC: H01L21/70 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L29/73 ,  H01L27/04

    Abstract: FI 9-81-044 METHOD FOR FORMING RECESSED ISOLATED REGIONS A method is described for forming the recessed dielectric isolation in a silicon substrate involves first forming trenches which are less than about 1 micron in depth in areas of one principal surface of the silcion substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region is formed in the substrate prior to the deposition of an epitaxial layer thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches are then oxidized in an oxidizing ambient to form a silicon dioxide layer thereon. A glass is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200.degree.C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.

    METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE
    15.
    发明专利
    METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE 未知

    公开(公告)号：CA1120605A

    公开(公告)日：1982-03-23

    申请号：CA337620

    申请日：1979-10-15

    Applicant: IBM

    Inventor： GARDINER JAMES R ,  PLISKIN WILLIAM A ,  REVITZ MARTIN ,  SHEPARD JOSEPH F

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/20

    Abstract: METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved. FI 9-77-065

Patent Agency Ranking