中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

41 records (took 0.019 seconds)

    METALLIZATION STRUCTURE
    11.
    发明专利
    METALLIZATION STRUCTURE 失效

    公开(公告)号：JPH10308362A

    公开(公告)日：1998-11-17

    申请号：JP11245598

    申请日：1998-04-22

    Applicant: IBM ,  TOSHIBA CORP

    Inventor： USUI TAKAMASA ,  DEHAVEN PATRICK W ,  RODBELL KENNETH P ,  FILIPPI RONALD G

    IPC: C23C14/14 ,  C23C16/06 ,  C23C28/02 ,  H01L21/28 ,  H01L21/285

    Abstract: PROBLEM TO BE SOLVED: To provide a metallization structure, which is small in resistivity, has excellent electricity transfer characteristics and at the same time, is textured to a high degree, and moreover, to prevent the formation of a hillock on the structure by a method wherein aluminium layers, aluminium alloy layers or both layers of the aluminium layers and the aluminum alloy layers, which come into contact electrically with tower group IVA metal layers having a thickness in a specified range, are formed. SOLUTION: Four or five-layer interconnected metallized layers are formed on interlayer stud connection layers 10, which are encircled with an insulator 8 and are connected with a silicon substratelike device substrate 6. Lower group IVA metal layers 13 consist of a titanium layer and the thickness of a metallization structure is about 90 to about 110 angstroms. By limiting this thickness, the structure of a metal layer, which is added afterwards, and the texture of the metal layer are controlled. Layers 15 to come into contact electrically with the lower layers 13 are aluminium layers or aluminium alloy layers. Titanium nitride layers 14 on the lower layers 13 prevent a reaction of the aluminium layers 15 with the lower layers 13 and capping layers consisting of titanium layers 18 and titanium nitride layers 19 perform an antireflection action.

    DAMASCENE MUTUAL CONNECTION WITH IMPROVED RELIABILITY AND ITS MANUFACTURE
    12.
    发明专利
    DAMASCENE MUTUAL CONNECTION WITH IMPROVED RELIABILITY AND ITS MANUFACTURE 失效

    公开(公告)号：JP2000100822A

    公开(公告)日：2000-04-07

    申请号：JP26415999

    申请日：1999-09-17

    Applicant: IBM ,  SIEMENS AG

    Inventor： CLEVENGER LARRY ,  FILIPPI JR RONALD G ,  GAMBINO JEFFREY ,  GIGNAC LYNNE ,  HURD JEFFERY L ,  HOINKIS MARK ,  IGGULDEN ROY C ,  MEHTER EBRAHIM ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN J

    IPC: H01L23/52 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To limit the forming quantity of an inter-metallic compound by sticking a wetting layer containing first metal which is brought into contact with an insulator to a recessed part, a uniform barrier layer on it, and a second metallic conduction layer on it at a temperature which is lower than that, at which the inter-metal compound is generated by means of diffusing first and second metals on the barrier layer. SOLUTION: Barrier layers 20 of nonreactive compounds are formed on wetting layers 18, where the metal of titanium(Ti) is evaporated by CVD on the sidewalls of the recessed parts 12 of an insulating layer 10 on the substrate 11 of a silicon water. The barrier layers 20 are formed of an arbitrary material, whose diffusion temperature of the constitution elements of the wetting layers 18 and the metallic layers, is higher than the reaction temperature of the constitution elements, and titanium nitride(TiN) is desirable. It is thicker than the sidewalls of the wetting layers 18 and is more uniform. Then, the recessed parts 12 are completely filled with the conduction layers a metal such as aluminum(Al). In the reaction between Ti of the wetting layers 18 and Al of the conduction layers 22, Ti and Al are unable to diffuse at a temperature lower than 430 deg.C, and they are brought into contact with each other and do not react.

    INTEGRATED CIRCUIT
    13.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11330244A

    公开(公告)日：1999-11-30

    申请号：JP9247299

    申请日：1999-03-31

    Applicant: SIEMENS AG ,  IBM

    Inventor： CLEVENGER LAWRENCE A ,  FILIPPI RONALD G ,  HOINKIS MARK ,  HURD JEFFERY L ,  IGGULDEN ROY C ,  PALM HERBERT ,  POETZLBERGER HANS W ,  RODBELL KENNETH P ,  SCHNABEL FLORIAN ,  WEBER STEFAN ,  MEHTER EBRAHIM A

    IPC: H01L21/28 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

    Abstract: PROBLEM TO BE SOLVED: To provide an interconnection with a damascene structure having an improved reliability, by using a liner for surrounding or sealing a conductor to give random crystal grain orientation to a conductive material. SOLUTION: A layer 137 is deposited on an insulating layer 130. A layer for lining the wall and the bottom of the contact opening functions as a base coat or liner for a conductive layer 138 to be subsequently deposited to fill the contact opening, and the degree of crystal grain orientation randomness of a material that fills the damascene structure is expanded. A parameter used for depositing a TiN layer is selected to expand the degree of base coat crystal grain orientation randomness and/or amorphous characteristics. The liner has an enough thickness to ensure the random crystal grain orientation of the conductive material to be subsequently deposited. Thus, the interconnection in an IC having the improved reliability can be obtained.

    Fet radiation monitor
    14.
    发明专利
    Fet radiation monitor 有权
    FET辐射监测器

    公开(公告)号：JP2011185933A

    公开(公告)日：2011-09-22

    申请号：JP2011047471

    申请日：2011-03-04

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： MICHAEL S GORDON ,  KOESTER STEVEN JOHN ,  RODBELL KENNETH P ,  YAU JENG-BANG

    IPC: G01T1/24 ,  H01L31/09

    CPC classification number: H01L31/119

    Abstract: PROBLEM TO BE SOLVED: To provide a method for radiation monitoring that obtains real time information concerning the amount of radiation.
    SOLUTION: A semiconductor device includes: a semiconductor substrate; a buried insulator layer disposed on the semiconductor substrate, the buried insulator layer configured to retain an amount of charge in a plurality of charge traps in response to a radiation exposure by the semiconductor device; a semiconductor layer disposed on the buried insulating layer; a second insulator layer disposed on the semiconductor layer; a gate conducting layer disposed on the second insulator layer; and one or more side contacts electrically connected to the semiconductor layer. The method for radiation monitoring includes: applying a backgate voltage to a radiation monitor, the radiation monitor comprising a field effect transistor (FET); exposing the radiation monitor to radiation; determining a change in a threshold voltage of the radiation monitor; and determining an amount of radiation exposure based on the change in threshold voltage.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种获得关于辐射量的实时信息的辐射监测方法。 解决方案：半导体器件包括：半导体衬底; 设置在所述半导体衬底上的掩埋绝缘体层，所述掩埋绝缘体层被配置为响应于所述半导体器件的辐射暴露而将多个电荷量保持在多个电荷阱中; 设置在所述掩埋绝缘层上的半导体层; 设置在所述半导体层上的第二绝缘体层; 设置在所述第二绝缘体层上的栅极导电层; 以及与半导体层电连接的一个或多个侧触点。 用于辐射监测的方法包括：将背栅电压施加到辐射监测器，所述辐射监测器包括场效应晶体管（FET）; 将辐射监测仪暴露于辐射; 确定辐射监测器的阈值电压的变化; 以及基于阈值电压的变化确定辐射暴露量。 版权所有（C）2011，JPO＆INPIT

    METHOD OF DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE
    17.
    发明申请
    METHOD OF DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE 审中-公开
    确定设计结构与行程粒子停止功率的方法

    公开(公告)号：WO2008082938A3

    公开(公告)日：2008-12-11

    申请号：PCT/US2007087766

    申请日：2007-12-17

    Applicant: IBM ,  FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

    Inventor： FIORENZA GIOVANNI ,  MURRAY CONAL E ,  RODBELL KENNETH P ,  TANG HENRY

    IPC: G06F17/50 ,  G06F7/62 ,  G06F19/00

    CPC classification number: G06F17/5009 ,  G06F2217/16

    Abstract: A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N interconnect layers into multiple pixels, and (iii) determining a first path of the traveling particle in a first interconnect layer of the N interconnect layers, (iv) identifying M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle, M being a positive integer, and (v) determining a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels.

    Abstract translation: 确定设计结构相对于行进粒子的停止能力的方法。 该方法包括（i）提供设计结构的设计信息，该设计结构包括包含N个互连层的后端行层，N是正整数，（ii）将N个互连层中的每个互连层分成多个像素 （iii）确定N个互连层中的第一互连层中的行进粒子的第一路径，（iv）识别在行进粒子的第一路径上的第一互连层的多个像素的M个路径像素，M （v）确定由于其完全穿过M个路径像素的第一像素而由行进粒子损失的第一损失能量。

    GROOVED POLISHING PADS AND METHODS OF USE
    18.
    发明申请
    GROOVED POLISHING PADS AND METHODS OF USE 审中-公开
    沟槽抛光垫和使用方法

    公开(公告)号：WO0202279A2

    公开(公告)日：2002-01-10

    申请号：PCT/US0120904

    申请日：2001-06-29

    Applicant: IBM ,  CHEN SHYNG TSONG ,  DAVIS KENNETH M ,  RODBELL KENNETH P

    Inventor： CHEN SHYNG-TSONG ,  DAVIS KENNETH M ,  RODBELL KENNETH P

    IPC: B24B37/26 ,  B24D13/12 ,  B24D13/14 ,  B24D18/00 ,  H01L21/304 ,  B24B37/04

    CPC classification number: B24B37/26 ,  B24D18/00

    Abstract: Grooves are formed in a CMP (12) pad by positioning the pad on a supporting surface with a working surface (22) of the pad in spaced relation opposite to a router bit (24) and at least one projecting stop member (33) adjacent to the router bit, an outer end portion of the bit projecting beyond the stop. When the bit is rotated, relative axial movement between the bit and the pad causes the outer end portion of the bit to cut an initial recess in the pad. Relative lateral movement between the rotating bit and the pad then forms a groove which extends laterally away from the recess and has a depth substantially the same as that of the recess. Different lateral movements between the bit and the pad are used to form a variety of groove patterns, the depths of which are precisely controlled by the stop member(s). The grooves may be formed in the polishing surface and/or the rear opposite surface of the pad and passages may be provided for interconnecting the rear grooves with the polishing surface or the front grooves. Grooves in the polishing surface may be provided with outlets through which a polishing slurry may flow while the polishing surface is in contact with a workpiece surface.

    Abstract translation: 通过将衬垫定位在支撑表面上，通过衬垫的工作表面（22）以与router刨机钻头（24）和至少一个相邻的突出的止动构件（33）相对的间隔关系相反的方式在CMP（12） 到router刨机钻头，钻头的外端部分突出到挡块之外。 当钻头旋转时，钻头和垫之间的相对轴向移动导致钻头的外端部分切割垫中的初始凹陷。 旋转钻头和垫之间的相对横向运动然后形成凹槽，该凹槽横向地远离凹槽延伸并且具有与凹槽基本相同的深度。 钻头和垫之间的不同横向运动用于形成各种凹槽图案，其深度由止挡构件精确控制。 凹槽可以形成在抛光表面和/或抛光垫的后部相对表面中，并且通道可以设置用于将后部凹槽与抛光表面或前部凹槽互连。 抛光表面中的凹槽可以设置有出口，在抛光表面与工件表面接触的同时抛光浆料可以流过出口。

Patent Agency Ranking