公开(公告)号：JP2000174027A

公开(公告)日：2000-06-23

申请号：JP34316599

申请日：1999-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  CABRAL JR CYRIL ,  CHRISTOPHER CARL PARKS ,  RODBELL KENNETH P ,  ROGER EN-RUEN TSUAI

IPC: H01L21/3205 ,  H01L21/265 ,  H01L21/283 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To improve the electromigration resistance characteristic by depositing a Cu seed layer to a housing region and implanting ions of a impurity selected among C, O, Cl, S and N in the seed layer. SOLUTION: In a simple damascene, a dopant ion is implanted in a Cu-rich conductive layer 90 before planarizing, the dopant is selected among C, O, Cl, S and N, a silicon nitride etch-planarize stop layer 92, a barrier layer 94 and a Cu seed layer 96 are formed in trenches formed on a semiconductor wafer or the side walls and top faces of openings, the ion implanting in the Cu conductive layer 90 is made in the single damascene process after the planarize stop, and the dopant brings about a microstructure unique to a conductor contg. large crystal grains, thereby improving the electromigration resistance characteristic.

公开(公告)号：JP2004158897A

公开(公告)日：2004-06-03

申请号：JP2004063897

申请日：2004-03-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  CABRAL JR CYRIL ,  CHRISTOPHER CARL PARKS ,  RODBELL KENNETH P ,  ROGER EN-RUEN TSUAI

IPC: H01L21/3205 ,  H01L21/265 ,  H01L21/283 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/2885 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To improve electromigration resistance of a copper electric conductor. SOLUTION: Impurities which improve the electromigraion resistance are added to the copper electric conductor after copper composition is deposited on inside a holding place. The impurities are C, O, C1, S and N, and a concentration level of the impurities is about 0.01ppm or about 1,000ppm. The impurities are made by electroplating copper after copper seed is deposited on inside the holding place and ion is implanted, or by electrodepositing the copper composition including the impurities and diffusing the impurities inside the copper seed layer after the copper layer is deposited, or by implanting dopant ion after the deposition of a barrier layer and then depositing the copper seed layer. Annealing is performed for diffusion. After the copper electric conductor is planarized, at least one element is ion-implanted into these surface layers. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提高铜导体的电迁移能力。 解决方案：将铜组合物沉积在保持位置之后，将改善耐电阻性的杂质加入到铜导电体中。 杂质为C，O，Cl，S和N，杂质浓度为约0.01ppm或约1,000ppm。 杂质通过将铜种子沉积在保持位置的内部并离子注入之后，或者通过电沉积包含杂质的铜组合物并在铜层沉积之后在铜籽晶层内扩散杂质，或通过植入 在沉积阻挡层之后然后沉积铜籽晶层的掺杂剂离子。 退火进行扩散。 在铜电导体平坦化之后，将至少一种元素离子注入到这些表面层中。 版权所有（C）2004，JPO

公开(公告)号：JP2009065207A

公开(公告)日：2009-03-26

申请号：JP2008314245

申请日：2008-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA J ,  UZOH CYPRIAN EMEKA ,  WONG KWONG-HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFREY LOUIS

IPC: H01L21/288 ,  C25D3/38 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing submicron interconnection structures for integrated circuits.
SOLUTION: A void-less and seamless conductor can be obtained by electro-plating copper (Cu) in an ordinary additive-containing bath used to plate flat, glossy, ductile, and low stress copper metal. This method capable of super-filling features without leaving voids or seams has a unique capability and is superior to any other methods. The electromigration resistance of a structure utilizing Cu electroplated by this method is superior to the electromigration resistance of an AlCu structure or a structure manufactured using copper deposited by any other method than electroplating.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造用于集成电路的亚微米互连结构的方法。

解决方案：通过在用于平板，光泽，延性和低应力铜金属的普通添加剂浴中电镀铜（Cu），可以获得无孔隙和无缝导体。 这种能够超级填充特征而不留下空隙或接缝的方法具有独特的能力并且优于任何其它方法。 利用这种方法电镀Cu的结构的电迁移电阻优于AlCu结构的电迁移电阻或使用除电镀之外的任何其它方法沉积的铜制成的结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2005136433A

公开(公告)日：2005-05-26

申请号：JP2004362864

申请日：2004-12-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA J ,  UZOH CYPRIAN EMEKA ,  WONG KWONG-HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFREY LOUIS

IPC: C25D3/38 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a submicron interconnection structure for an integrated circuit.
SOLUTION: By electroplating Cu in a bath which includes an additive and is usually used for adhering Cu metal which is flat and glossy and has high ductility and low stress, seamless semiconductor without void is obtained. This method allows a feature to be super-filled up without leaving void or seam. The resistance of electromigration with the structure utilizing Cu which is electroplated by this method is more excellent than the resistance of electromigration with the structure manufactured using Cu which is adhered by methods other than AlCu structure or electroplating.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于集成电路的亚微米互连结构的制造方法。 解决方案：通过在包含添加剂的浴中电镀Cu，通常用于粘附平坦且光滑且具有高延展性和低应力的Cu金属，获得无空隙的无缝半导体。 这种方法允许特征被超填充而不留下空隙或接缝。 利用该方法电镀Cu结构的电迁移电阻比使用除AlCu结构或电镀以外的方法附着的Cu制造的结构的电迁移电阻更好。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：AU1330897A

公开(公告)日：1998-07-15

申请号：AU1330897

申请日：1996-12-16

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA JEAN ,  UZOH CYPRIAN EMEKA ,  WONG KWONG HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFERY LOUIS

IPC: C25D7/12 ,  H01L21/28 ,  H01L21/288 ,  H01L21/768 ,  H01L23/532

Abstract: A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches.

公开(公告)号：DE69104671T2

公开(公告)日：1995-05-04

申请号：DE69104671

申请日：1991-08-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  CHANG JEI-WEI ,  PETEK BOJAN ,  ROMANKIW LUBOMYR

IPC: G11B5/127 ,  G11B5/187 ,  G11B5/31 ,  G11B5/39 ,  H01F10/32 ,  H01F10/08 ,  G11B5/33

Abstract: A magnetic thin film structure comprising a first layer (12) of magnetic material having a low anisotropy Hk magnetically coupled to a second layer (14) magnetic material having a high anisotropy Hk and a low coercivity. The laminate provides a dual anisotropy behavior such that the laminate exhibits a high initial permeability at relatively small applied fields during the read operation and a high anisotropy at high applied fields during the write operation. The laminate of the present invention reduces inductive head domain instability produced by the write operation while maintaining high reproducing sensitivity during the read operation. Use of the higher Hk material also reduces the sensitivity of the head performance to variation in process-induced stresses.

公开(公告)号：IE960846A1

公开(公告)日：1997-09-24

申请号：IE960846

申请日：1996-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DATTA MADAV ,  DELIGIANNI HARIKLIA ,  HORKANS WILMA JEAN ,  KANG SUNG KWON ,  KWIETNIAK KEITH THOMAS ,  MATHAD GANGADHARA SWAMI ,  PURUSHOTHAMAN SAMPATH ,  SHI LEATHEN ,  TONG HO-MING

IPC: B23K35/26 ,  B23K35/00 ,  B32B15/01 ,  C22C13/00 ,  C22C13/02 ,  H01L21/60 ,  H01L23/485 ,  H01L23/488

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe, and NiCoFe on the adhesion/barrier layer, and lead free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

公开(公告)号：IE79088B1

公开(公告)日：1998-04-08

申请号：IE960846

申请日：1996-12-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DATTA MADAV ,  DELIGIANNI HARIKLIA ,  HORKANS WILMA JEAN ,  KANG SUNG KWON ,  KWIETNIAK KEITH THOMAS ,  MATHAD GANGADHARA SWAMI ,  PURUSHOTHAMAN SAMPATH ,  SHI LEATHEN ,  TONG HO-MING

IPC: B23K35/26 ,  B23K35/00 ,  B32B15/01 ,  C22C13/00 ,  C22C13/02 ,  H01L21/60 ,  H01L23/485 ,  H01L23/488

Abstract: An interconnection structure suitable for the connection of microelectronic circuit chips to packages is provided by this invention. In particular, the invention pertains to the area-array or flip-chip technology often called C4 (controlled collapse chip connection). The structure comprises an adhesion/barrier layer deposited on a passivated substrate (e.g., a silicon wafer), optionally an additional adhesion layer, a solderable layer of a metal selected from the group consisting of Ni, Co, Fe, NiFe, NiCo, CoFe and NiCoFe on the adhesion/barrier layer, and a lead-free solder ball comprising tin as the predominate component and one or more alloying elements selected from Bi, Ag, and Sb, and further optionally including one or more elements selected from the group consisting of Zn, In, Ni, Co and Cu.

公开(公告)号：DE69104671D1

公开(公告)日：1994-11-24

申请号：DE69104671

申请日：1991-08-02

Applicant: IBM

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  CHANG JEI-WEI ,  PETEK BOJAN ,  ROMANKIW LUBOMYR

IPC: G11B5/127 ,  G11B5/187 ,  G11B5/31 ,  G11B5/39 ,  H01F10/32 ,  H01F10/08 ,  G11B5/33

Abstract: A magnetic thin film structure comprising a first layer (12) of magnetic material having a low anisotropy Hk magnetically coupled to a second layer (14) magnetic material having a high anisotropy Hk and a low coercivity. The laminate provides a dual anisotropy behavior such that the laminate exhibits a high initial permeability at relatively small applied fields during the read operation and a high anisotropy at high applied fields during the write operation. The laminate of the present invention reduces inductive head domain instability produced by the write operation while maintaining high reproducing sensitivity during the read operation. Use of the higher Hk material also reduces the sensitivity of the head performance to variation in process-induced stresses.