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    SCHATTENMASKEN-SEITENWAND-TUNNELKONTAKT FÜR DIE QUANTENDATENVERARBEITUNG
    11.
    发明专利
    SCHATTENMASKEN-SEITENWAND-TUNNELKONTAKT FÜR DIE QUANTENDATENVERARBEITUNG 未知

    公开(公告)号：DE112017007386T5

    公开(公告)日：2019-12-12

    申请号：DE112017007386

    申请日：2017-12-19

    Applicant: IBM

    Inventor： ROSENBLATT SAMI ,  BRINK MARKUS

    IPC: H01L39/22

    Abstract: Eine Technik bezieht sich auf ein Bilden eines Seitenwand-Tunnelkontakts. Eine erste leitende Schicht wird durch eine erste Schattenmaskenbedampfung gebildet. Eine zweite leitende Schicht wird auf einem Teil der ersten leitenden Schicht gebildet, wobei die zweite leitende Schicht durch eine zweite Schattenmaskenbedampfung gebildet wird. Eine Oxidschicht wird auf der ersten leitenden Schicht und der zweiten leitenden Schicht gebildet. Eine dritte leitende Schicht wird auf einem Teil der Oxidschicht gebildet, sodass sich der Seitenwand-Tunnelkontakt zwischen der ersten leitenden Schicht und der dritten leitenden Schicht befindet.

    Fabricating transmon qubit flip-chip structures for quantum computing devices
    12.
    发明专利
    Fabricating transmon qubit flip-chip structures for quantum computing devices 未知

    公开(公告)号：IL288976D0

    公开(公告)日：2022-02-01

    申请号：IL28897621

    申请日：2021-12-13

    Applicant: IBM ,  CHOW JERRY ,  ROSENBLATT SAMI

    Inventor： CHOW JERRY ,  ROSENBLATT SAMI

    IPC: G06N10/00 ,  H01L27/18 ,  H01L39/04 ,  H01L39/22 ,  H01L39/24

    Abstract: A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

    Metodologia de viés de fluxo persistente para circuitos fechados supercondutores
    13.
    发明专利
    Metodologia de viés de fluxo persistente para circuitos fechados supercondutores 未知

    公开(公告)号：BR112021021289A2

    公开(公告)日：2022-01-18

    申请号：BR112021021289

    申请日：2020-03-27

    Applicant: IBM

    Inventor： SANDBERG MARTIN ,  RASIT ONUR TOPALOGLU ,  ROSENBLATT SAMI

    IPC: H01L27/18 ,  G06N10/00 ,  H01L39/12 ,  H03K19/195

    Abstract: metodologia de viés de fluxo persistente para circuitos fechados supercondutores. um dispositivo qubit ajustável inclui um qubit ajustável, o qubit ajustável incluindo um circuito fechado de dispositivo de interferência quântica supercondutor (squid). o dispositivo de qubit ajustável inclui ainda um circuito fechado supercondutor indutivo acoplado ao circuito fechado squid, e uma linha de viés de fluxo indutivamente acoplada ao circuito fechado supercondutor. o circuito fechado supercondutor inclui um material supercondutor com uma temperatura crítica que é uma temperatura mais baixa do que uma temperatura crítica de qualquer material supercondutor do qubit ajustável. em operação, o circuito fechado supercondutor fornece um viés persistente ao qubit ajustável.

    PERSISTENT FLUX BIASING METHODOLOGY FOR SUPERCONDUCTING LOOPS
    15.
    发明专利
    PERSISTENT FLUX BIASING METHODOLOGY FOR SUPERCONDUCTING LOOPS 未知

    公开(公告)号：SG11202109840WA

    公开(公告)日：2021-10-28

    申请号：SG11202109840W

    申请日：2020-03-27

    Applicant: IBM

    Inventor： SANDBERG MARTIN ,  ROSENBLATT SAMI ,  TOPALOGLU RASIT

    IPC: G06N10/00 ,  H01L27/18 ,  H01L39/12 ,  H03K19/195

    Abstract: A tunable qubit device includes a tunable qubit, the tunable qubit including a superconducting quantum interference device (SQUID) loop. The tunable qubit device further includes a superconducting loop inductively coupled to the SQUID loop, and a flux bias line inductively coupled to the superconducting loop. The superconducting loop includes a superconducting material having a critical temperature that is a lower temperature than a critical temperature of any superconducting material of the tunable qubit. In operation, the superconducting loop provides a persistent bias to the tunable qubit.

    Fabricating transmon qubit flip-chip structures for quantum computing devices
    16.
    发明专利
    Fabricating transmon qubit flip-chip structures for quantum computing devices 未知

    公开(公告)号：AU2020296882A1

    公开(公告)日：2021-10-14

    申请号：AU2020296882

    申请日：2020-06-15

    Applicant: IBM

    Inventor： CHOW JERRY ,  ROSENBLATT SAMI

    IPC: H01L27/18 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

    Abstract: A quantum computing device (300) is formed using a first chip (302) and a second chip (306), the first chip having a first substrate (303), a first set of pads (312 A,B), and a set of Josephson junctions (304) disposed on the first substrate. The second chip has a second substrate (307), a second set of pads (308) disposed on the second substrate opposite the first set of pads, and a second layer (310 A, B) formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

    Self-authenticating chip
    18.
    发明专利
    Self-authenticating chip 未知

    公开(公告)号：GB2509823B

    公开(公告)日：2015-11-11

    申请号：GB201320411

    申请日：2013-11-19

    Applicant: IBM

    Inventor： KIRIHATA TOSHIAKI ,  CHELLAPPA SRIVATSAN ,  IYER SUBRAMANIAN ,  ROSENBLATT SAMI

    IPC: G06F21/44 ,  G06F21/30

    Abstract: Embodiments of the present invention provide an authenticating service of a chip having an intrinsic identifier (ID). In a typical embodiment, an authenticating device is provided that includes an identification (ID) engine, a self-test engine, and an intrinsic component. The intrinsic component is associated with a chip and includes an intrinsic feature. The self-test engine retrieves the intrinsic feature and communicates it to the identification engine. The identification engine receives the intrinsic feature, generates a first authentication value using the intrinsic feature, and stores the authentication value in memory. The self-test engine generates a second authentication value using an authentication challenge. The identification engine includes a compare circuitry that compares the first authentication value and the second authentication value and generates an authentication output value based on the results of the compare of the two values.

    RETENTION BASED INTRINSIC FINGERPRINT IDENTIFICATION FEATURING A FUZZY ALGORITHM AND A DYNAMIC KEY
    19.
    发明专利
    RETENTION BASED INTRINSIC FINGERPRINT IDENTIFICATION FEATURING A FUZZY ALGORITHM AND A DYNAMIC KEY 未知

    公开(公告)号：IN2203CHN2014A

    公开(公告)日：2015-06-12

    申请号：IN2203CHN2014

    申请日：2014-03-21

    Applicant: IBM

    Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROBSON NORMAN W ,  ROSENBLATT SAMI

    IPC: G11C29/00 ,  G06F21/00

    Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails adjusted by a BIST engine 625 wherein the fail numbers 803 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation resulting in a more secure identification.

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