公开(公告)号：DE69307274T2

公开(公告)日：1997-07-17

申请号：DE69307274

申请日：1993-10-05

Applicant: IBM

Inventor： BUTI TAQI N ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F ,  HSU LOUIS LU-CHEN

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/535

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：BR9405158A

公开(公告)日：1995-08-01

申请号：BR9405158

申请日：1994-12-20

Applicant: IBM

Inventor： GALLI CAROL ,  HSU LOUIS L ,  OGURA SEIKI ,  SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L27/08

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. First, a trench (18) is formed in a silicon substrate (12) having a thin blanket layer (14) of a hard polish-stop material and a photo resist layer (16) (used to pattern the structure) formed thereon. A channel stop region (20) is formed as standard in the trench. Next, the trench is filled with SiO2 using liquid phase oxide deposition above the level of said thin layer. Then the photo resist layer is removed and the SiO2 fill (22) is planarized. Finally, the SiO2 fill is densified and during the thermal cycle, a thin layer (30) of thermal oxide is formed at the fill-substrate interface. The structure can be readily and easily planarized, and voids contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on the resist used to form the trench.

公开(公告)号：CA1166762A

公开(公告)日：1984-05-01

申请号：CA404056

申请日：1982-05-28

Applicant: IBM

Inventor： PLISKIN WILLIAM A ,  RISEMAN JACOB ,  SHEPARD JOSEPH F

IPC: H01L21/70 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L29/73 ,  H01L27/04

Abstract: FI 9-81-044 METHOD FOR FORMING RECESSED ISOLATED REGIONS A method is described for forming the recessed dielectric isolation in a silicon substrate involves first forming trenches which are less than about 1 micron in depth in areas of one principal surface of the silcion substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region is formed in the substrate prior to the deposition of an epitaxial layer thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches are then oxidized in an oxidizing ambient to form a silicon dioxide layer thereon. A glass is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200.degree.C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.

公开(公告)号：CA1120605A

公开(公告)日：1982-03-23

申请号：CA337620

申请日：1979-10-15

Applicant: IBM

Inventor： GARDINER JAMES R ,  PLISKIN WILLIAM A ,  REVITZ MARTIN ,  SHEPARD JOSEPH F

IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L29/417 ,  H01L29/778 ,  H01L21/20

Abstract: METAL-INSULATOR-SEMICONDUCTOR DEVICE MANUFACTURE A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved. FI 9-77-065

公开(公告)号：DE10352068B4

公开(公告)日：2006-10-05

申请号：DE10352068

申请日：2003-11-07

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL ,  SHEPARD JOSEPH F

IPC: H01L21/8242 ,  H01L21/308 ,  H01L21/334 ,  H01L27/108 ,  H01L29/94 ,  H04J1/16 ,  H04J3/14

Abstract: A semiconductor device is fabricated using a micro-masking structure. The micro-masking structure is formed along the sidewalls of a trench in a semiconductor substrate or along the sidewalls of an electrode disposed over the semiconductor substrate. The micro-masking structure exposes portions of the sidewalls and covers other portions of the sidewalls. Then the exposed portions of the sidewalls are recessed to form a plurality of recesses such that the sidewalls have an increase surface area. After the recessing, the micro-masking structure is removed. The recessed sidewalls provide enhanced capacitance.

公开(公告)号：CA2105039A1

公开(公告)日：1994-05-07

申请号：CA2105039

申请日：1993-08-27

Applicant: IBM

Inventor： BUTI TAQI N ,  HSU LOUIS L ,  JOSHI RAJIV V ,  SHEPARD JOSEPH F

IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/441 ,  H01L21/44 ,  H01L21/48

Abstract: A wafer structure (10) suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate (20) having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads (24) of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads (22) of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps (28) of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate (30) having an oxide layer (32) thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

公开(公告)号：DE3572418D1

公开(公告)日：1989-09-21

申请号：DE3572418

申请日：1985-05-23

Applicant: IBM

Inventor： SHEPARD JOSEPH F

IPC: H01L21/76 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3215 ,  H01L21/763

Abstract: The method of planarizing polysilicon-filled trenches involves first filling the trenches (12) with an undoped polysilicon (14) until the upper surface (18) is substantially planar. The polycrystalline silicon (14) is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth (16), level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon (16) and leaves the undoped polysilicon (17) untouched in the trenches (12).