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公开(公告)号：CA992212A
公开(公告)日：1976-06-29
申请号：CA172497
申请日：1973-05-28
Applicant: IBM
Inventor： DESIMONE ROY R , DONOFRIO NICHOLAS M , LINTON RICHARD H , SONODA GEORGE , WADE WILLIAM T
IPC: G11C11/412 , G11C8/04 , G11C8/16 , G11C11/402 , G11C11/406
Abstract: An electronic data storage which operates as a DC stable storage array, but retains the advantages of an AC stable storage cell circuit. The AC stable storage cells are regenerated at a frequency asynchronous with respect to the storage cycle time. Gating means inhibit the regenerating signals when the system desires access, thereby permitting the storage cells to be accessed for information at any time in a completely random access mode.
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公开(公告)号：DE2359647A1
公开(公告)日：1974-07-04
申请号：DE2359647
申请日：1973-11-30
Applicant: IBM
Inventor： LEE JAMES MINDA , SONODA GEORGE
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公开(公告)号：FR2316696A1
公开(公告)日：1977-01-28
申请号：FR7615014
申请日：1976-05-13
Applicant: IBM
Inventor： SONODA GEORGE
IPC: G11C11/412 , G11C11/40
Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. The load devices are never fully turned off so that complete D.C. stability is achieved with a four device cell because no one cell in an array of memory cells ever goes into a data retention mode.
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公开(公告)号：FR2296243A1
公开(公告)日：1976-07-23
申请号：FR7534720
申请日：1975-11-05
Applicant: IBM
Inventor： ASKIN HALUK O , JACOBSON EDWARD C , LEE JAMES M , SONODA GEORGE
IPC: G11C11/412 , G11C11/40
Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.
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公开(公告)号：DE2556832A1
公开(公告)日：1976-06-24
申请号：DE2556832
申请日：1975-12-17
Applicant: IBM
Inventor： SONODA GEORGE
IPC: G11C11/412 , G11C7/00 , G11C11/40 , H01L29/76
Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.
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Patent Agency Ranking
公开(公告)号：DE2301855A1
公开(公告)日：1973-08-16
申请号：DE2301855
申请日：1973-01-15
Applicant: IBM
Inventor： LUCKETT GARY CLAIR , SONODA GEORGE
IPC: H03K19/0185 , H03K5/00
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公开(公告)号：DE1959689A1
公开(公告)日：1970-06-18
申请号：DE1959689
申请日：1969-11-28
Applicant: IBM
Inventor： SONODA GEORGE
IPC: G11C11/41 , G11C11/34 , G11C11/402 , G11C11/412 , G11C11/417 , G11C11/418 , H03K3/356 , G11C11/40
Abstract: 1,253,397. Transistor bi-stable circuits. INTERNATIONAL BUSINESS MACHINES CORP. 6 Nov., 1969 [5 Dec., 1968], No. 54365/69. Heading H3T. [Also in Division G4] Each one of a cross-coupled semi-conductor pair Q1, Q2 has a load consisting of two FET's Q5, Q7 and Q6, Q8, the FET's of each pair being rendered conductive at different times so as to represent a high load impedance to Q1, Q2. An oscillator 10 switches on Q7 and Q8 at the same time as it switches off Q5, Q6, and vice-versa. The supply A, which is one of the oscillator outputs, thus first charges the electrode capacitances C7, C8 and these in turn charge C1, C2 to voltages dependent upon which of Q1, Q2 is on. To read the state of Q1, Q2 a pulse on line 16 turns on Q3, Q4 to connect the drains of Q1, Q2 to lines 12, 14 which are maintained positive enough (+4v.) to prevent destruction of the state. To write, the line 16 is again pulsed to turn on Q3, Q4 and one of the lines 12, 14 is lowered to 0v. A matrix of the cross-coupled circuits may be used (Fig. 3, not shown).
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公开(公告)号：DE2556831A1
公开(公告)日：1976-06-24
申请号：DE2556831
申请日：1975-12-17
Applicant: IBM
Inventor： ASKIN HALUK O , JACOBSON EDWARD C , LEE JAMES M , SONODA GEORGE
IPC: G11C11/412 , G11C7/00 , G11C11/40 , H01L29/76
Abstract: Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross-coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.
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公开(公告)号：FR2276661A1
公开(公告)日：1976-01-23
申请号：FR7516532
申请日：1975-05-21
Applicant: IBM
Inventor： CHU WILLIAM M , SONODA GEORGE
IPC: G11C11/413 , G06F11/22 , G11C11/412 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/50 , G11C29/56
Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.
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公开(公告)号：DE2527486A1
公开(公告)日：1976-01-15
申请号：DE2527486
申请日：1975-06-20
Applicant: IBM
Inventor： CHU WILLIAM M , SONODA GEORGE
IPC: G11C11/413 , G06F11/22 , G11C11/412 , G11C29/00 , G11C29/04 , G11C29/14 , G11C29/50 , G11C29/56 , G11C7/00
Abstract: Disclosed is a technique for testing electronic storage arrays including bistable storage cells fabricated in accordance with integrated semiconductor technology. Also described is the testing of load devices in a flip flop storage cell which is connected to a pair of bit lines that are inaccessible for the direct application of test signals. Testing is performed by altering the time duration of signals applied to the memory cells under test.
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